CD4031BMS Datasheet PDF - Intersil Corporation
| Part Number | CD4031BMS | |
| Description | CMOS 64-Stage Static Shift Register | |
| Manufacturers | Intersil Corporation | |
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CD4031BMS
December 1992
CMOS 64-Stage Static Shift Register
Features
Description
• High Voltage Type (20V Rating)
• Fully Static Operation: DC to 12MHz (typ.) at VDD -
VSS = 15V
• Standard TTL Drive Capability on Q Output
• Recirculation Capability
• Three Cascading Modes:
- Direct Clocking for High-Speed Operation
- Delayed Clocking for Reduced Clock Drive Require-
ments
- Additional 1/2 Stage for Slow Clocks
• 100% Tested For Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full
Package-Temperature Range;
- 100nA at 18V and +25oC
• Noise Margin (Over Full Package Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Applications
• Serial Shift Registers
• Time Delay Circuits
The CD4031BMS is a static shift register that contains 64 D-
type, master-slave flip-flop stages and one stage which is a
D-type master flip-flop only (referred to as a 1/2 stage).
The logic level present at the DATA input is transferred into
the first stage and shifted one stage at each positive-going
clock transition. Maximum clock frequencies up to 12MHz
(typical) can be obtained. Because fully static operation is
allowed, information can be permanently stored with the
clock line in either the low or high state. The CD4031BMS
has a MODE CONTROL input that, when in the high state,
allows operation in the recirculating mode. The MODE CON-
TROL input can also be used to select between two sepa-
rate data sources. Register packages can be cascaded and
the clock lines driven directly for high-speed operation. Alter-
natively, a delayed clock output (CLD) is provided that
enables cascading register packages while allowing reduced
clock drive fan-out and transition-time requirements. A third
cascading option makes use of the Q’ output from the 1/2
stage, which is available on the next negative-going transi-
tion of the clock after the Q output occurs. This delayed out-
put, like the delayed clock CLD, is used with clocks having
slow rise and fall times.
The CD4031BMS is supplied in these 16 lead outline pack-
ages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4X
H1F
H6W
Pinout
CD4031BMS
TOP VIEW
RECIRCULATE
DATA IN 2 1
CLOCK INHIBIT 2
NC 3
NC 4
Q’ 5
Q6
Q7
VSS 8
16 VDD
15 DATA IN 1
14 NC
13 NC
12 NC
11 NC
10 MODE CONTROL
9 CLD
NC = NO CONNECTION
Functional Diagram
DATA 1 15
IN
MODE 10
CONT.
RECIRC 1
DATA 2
IN
CONTROL
LOGIC
CLOCK 2
IN
CLOCK
LOGIC
64
STAGES
DATA
OUT
6
DATA
OUT
CL 7
CL
9
DELAYED
VDD = 16
VSS = 8
CLOCK
OUT
NC = 3, 4, 11, 12, 13, 14
1/2
STAGE
Q’
5
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-816
File Number 3306
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| |
 
Specifications CD4031BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
PARAMETER
SYMBOL
CONDITIONS
NOTES TEMPERATURE MIN MAX UNITS
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. If more than one unit is cascaded in the parallel clocked application, TRCL should be made ≤ the sum of the propagation delay at 50pF
and the transition time of the output driving stage.
5. Maximum clock frequency for cascaded units;
a) Using Delayed Clock feature in recirculation mode:
FMAX = --(--n------1---)---C----L---,---p---r--o---p----d---e---l-a---y-----a---n---d----Q----1--p---r-o---p-----d---e---l-a---y----a---n---d----s---e---t---–-----u---p----t-i--m----e- where n = number of packages
b) Not using Delayed Clock:
FMAX = --------------------------------------1--------------------------------------
propagation delay and set – up time
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
N Threshold Voltage
N Threshold Voltage
Delta
P Threshold Voltage
P Threshold Voltage
Delta
Functional
Propagation Delay Time
SYMBOL
CONDITIONS
IDD VDD = 20V, VIN = VDD or GND
VNTH VDD = 10V, ISS = -10µA
∆VNTH VDD = 10V, ISS = -10µA
VPTH VSS = 0V, IDD = 10µA
∆VPTH VSS = 0V, IDD = 10µA
F
TPHL
TPLH
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
VDD = 5V (Worst Case)
NOTES
1, 4
1, 4
1, 4
1, 4
1, 4
1
1, 2, 3, 4
TEMPERATURE
+25oC
+25oC
+25oC
MIN
-
-2.8
-
MAX
25
-0.2
±1
+25oC
+25oC
0.2 2.8
- ±1
+25oC
+25oC
VOH > VOL <
VDD/2 VDD/2
- 1.35 x
+25oC
Limit
NOTES:
1. All voltages referenced to device GND.
2. VDD = 5V, CL = 50pF, RL = 200K
3. See Table 2 for +25oC limit.
UNITS
µA
V
V
V
V
V
ns
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC
PARAMETER
SYMBOL
DELTA LIMIT
Supply Current - MSI-2
Output Current (Sink)
IDD
IOL5
± 1.0µA
± 20% x Pre-Test Reading
7-820
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| Information | Total 10 Pages | |
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