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PDF CD4043BMS Data sheet ( Hoja de datos )
| Número de pieza | CD4043BMS | |
| Descripción | CMOS Quad Clocked D Latch | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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CD4043BMS
CD4044BMS
December 1992
CMOS Quad 3 State R/S Latches
Features
Pinout
• High Voltage Types (20V Rating)
• Quad NOR R/S Latch- CD4043BMS
• Quad NAND R/S Latch - CD4044BMS
• 3 State Outputs with Common Output ENABLE
• Separate SET and RESET Inputs for Each Latch
• NOR and NAND Configuration
• 5V, 10V and 15V Parametric Ratings
• Standardized Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µa at 18V Over Full Pack-
age-Temperature Range;
- 100nA at 18V and 25oC
• Noise Margin (Over Full Package Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of ‘B’
Series CMOS Devices”
Applications
• Holding Register in Multi-Register System
• Four Bits of Independent Storage with Output ENABLE
• Strobed Register
• General Digital Logic
• CD4043BMS for Positive Logic Systems
• CD4044BMS for Negative Logic Systems
Description
CD4043BMS types are quad cross-coupled 3-state CMOS NOR
latches and the CD4044BMS types are quad cross-coupled 3-
state CMOS NAND latches. Each latch has a separate Q output
and individual SET and RESET inputs. The Q outputs are con-
trolled by a common ENABLE input. A logic “1” or high on the
ENABLE input connects the latch states to the Q outputs. A logic
“0” or low on the ENABLE input disconnects the latch states from
the Q outputs, results in an open circuit feature allows common
busing of the outputs.
The CD4043BMS and CD4044BMS are supplied in these 16-
lead outline packages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
*CD4043B Only
*H4T †H4T
*H1C †HIE
*H3X †H6W
†CD4044B Only
CD4043BMS
TOP VIEW
Q4 1
Q1 2
R1 3
S1 4
ENABLE 5
S2 6
R2 7
VSS 8
16 VDD
15 R4
14 S4
13 NC
12 S3
11 R3
10 Q3
9 Q2
NC = NO CONNECTION
CD4044BMS
TOP VIEW
Q4 1
NC 2
S1 3
R1 4
ENABLE 5
R2 6
S2 7
VSS 8
16 VDD
15 S4
14 R4
13 Q1
12 R3
11 S3
10 Q3
9 Q2
NC = NO CONNECTION
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-876
File Number 3311
1 page  
Specifications CD4043BMS, CD4044BMS
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUP
MIL-STD-883
METHOD
GROUP A SUBGROUPS
Initial Test (Pre Burn-In)
100% 5004
1, 7, 9
Interim Test 1 (Post Burn-In)
100% 5004
1, 7, 9
Interim Test 2 (Post Burn-In)
100% 5004
1, 7, 9
PDA (Note 1)
100% 5004
1, 7, 9, Deltas
Interim Test 3 (Post Burn-In)
100% 5004
1, 7, 9
PDA (Note 1)
100% 5004
1, 7, 9, Deltas
Final Test
100% 5004
2, 3, 8A, 8B, 10, 11
Group A
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group B
Subgroup B-5
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Subgroup B-6
Sample 5005
1, 7, 9
Group D
Sample 5005
1, 2, 3, 8A, 8B, 9
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
READ AND RECORD
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
CONFORMANCE GROUPS
Group E Subgroup 2
TABLE 7. TOTAL DOSE IRRADIATION
MIL-STD-883
METHOD
TEST
PRE-IRRAD
POST-IRRAD
5005
1, 7, 9
Table 4
READ AND RECORD
PRE-IRRAD
POST-IRRAD
1, 9 Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
OPEN
GROUND
VDD
9V ± -0.5V
50kHz
25kHz
PART NUMBER CD4043BMS
Static Burn-In 1
Note 1
1, 2, 9, 10, 13
3 - 8, 11, 12, 14,
15
16
Static Burn-In 2
Note 1
1, 2, 9, 10, 13
8
3 - 7, 11, 12,
14 - 16
Dynamic Burn-
In Note 1
13
8
5, 16
1, 2, 9, 12
4, 6, 12, 14
3, 7, 11, 15
Irradiation
Note 2
1, 2, 9, 10, 13
8
3 - 7, 11, 12,
14 - 16
PART NUMBER CD4044BMS
Static Burn-In 1
Note 1
1, 2, 9, 10, 13
3 - 8, 11, 12, 14,
15
16
Static Burn-In 2
Note 1
1, 2, 9, 10, 13
8
3 - 7, 11, 12,
14 - 16
Dynamic Burn-
In Note 1
2
8
5, 16
1, 9, 10, 13
4, 6, 12, 14
3, 7, 11, 15
Irradiation
Note 2
1, 2, 9, 10, 13
8
3 - 7, 11, 12,
14 - 16
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD
= 10V ± 0.5V
7-880
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet CD4043BMS.PDF ] | |
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