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PDF CD4046BC Data sheet ( Hoja de datos )
| Número de pieza | CD4046BC | |
| Descripción | Micropower Phase-Locked Loop | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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November 1995
CD4046BM CD4046BC Micropower Phase-Locked Loop
General Description
The CD4046B micropower phase-locked loop (PLL) con-
sists of a low power linear voltage-controlled oscillator
(VCO) a source follower a zener diode and two phase
comparators The two phase comparators have a common
signal input and a common comparator input The signal
input can be directly coupled for a large voltage signal or
capacitively coupled to the self-biasing amplifier at the sig-
nal input for a small voltage signal
Phase comparator I an exclusive OR gate provides a digital
error signal (phase comp I Out) and maintains 90 phase
shifts at the VCO center frequency Between signal input
and comparator input (both at 50% duty cycle) it may lock
onto the signal input frequencies that are close to harmon-
ics of the VCO center frequency
Phase comparator II is an edge-controlled digital memory
network It provides a digital error signal (phase comp II
Out) and lock-in signal (phase pulses) to indicate a locked
condition and maintains a 0 phase shift between signal in-
put and comparator input
The linear voltage-controlled oscillator (VCO) produces an
output signal (VCO Out) whose frequency is determined by
the voltage at the VCOIN input and the capacitor and resis-
tors connected to pin C1A C1B R1 and R2
The source follower output of the VCOIN (demodulator Out)
is used with an external resistor of 10 kX or more
The INHIBIT input when high disables the VCO and source
follower to minimize standby power consumption The zener
diode is provided for power supply regulation if necessary
Features
Y Wide supply voltage range
3 0V to 18V
Y Low dynamic
power consumption
Y VCO frequency
Y Low frequency drift
with temperature
70 mW (typ ) at
fo e 10 kHz VDD e 5V
1 3 MHz (typ ) at VDD e 10V
0 06% C at VDD e 10V
Y High VCO linearity
1% (typ )
Applications
Y FM demodulator and modulator
Y Frequency synthesis and multiplication
Y Frequency discrimination
Y Data synchronization and conditioning
Y Voltage-to-frequency conversion
Y Tone decoding
Y FSK modulation
Y Motor speed control
Block Connection Diagrams
Dual-In-Line Package
FIGURE 1
C1995 National Semiconductor Corporation TL F 5968
Top View
TL F 5968 – 2
Order Number CD4046B
TL F 5968 – 1
RRD-B30M115 Printed in U S A
1 page  
AC Electrical Characteristics CD4046BM CD4046BC TA e 25 C CL e 50 pF (Continued)
Symbol
Parameter
Conditions
Min Typ
Max
PHASE COMPARATORS SECTION
RIN Input Resistance
Signal Input
Comparator Input
AC-Coupled Signal Input Voltage
Sensitivity
DEMODULATOR OUTPUT
VDD e 5V
VDD e 10V
VDD e 15V
VDD e 5V
VDD e 10V
VDD e 15V
CSERIES e 1000 pF
f e 50 kHz
VDD e 5V
VDD e 10V
VDD e 15V
13
02 07
01 03
106
106
106
200 400
400 800
700 1400
VCOINb
VDEM
Offset Voltage
Linearity
ZENER DIODE
RS t 10 kX VDD e 5V
RS t 10 kX VDD e 10V
RS t 50 kX VDD e 15V
RS t 50 kX
VCOIN e 2 5V g0 3V VDD e 5V
VCOIN e 5V g2 5V VDD e 10V
VCOIN e 7 5V g5V VDD e 15V
1 50 2 2
1 50 2 2
1 50 2 2
01
06
08
VZ Zener Diode Voltage
IZ e 50 mA
RZ Zener Dynamic Resistance IZ e 1 mA
63 70
100
77
AC Parameters are guaranteed by DC correlated testing
Units
MX
MX
MX
MX
MX
MX
mV
mV
mV
V
V
V
%
%
%
V
X
5
5 Page 
Design Information
This information is a guide for approximating the value of
external components for the CD4046B in a phase-locked-
loop system The selected external components must be
within the following ranges R1 R2 t 10 kX RS t 10 kX
C1 t 50 pF
In addition to the given design information refer to Figure 5
for R1 R2 and C1 component selections
Characteristics
VCO Frequency
Using Phase Comparator I
VCO Without Offset
R2 e %
VCO With Offset
Using Phase Comparator II
VCO Without Offset
R2 e %
VCO With Offset
For No Signal Input
Frequency Lock
Range 2 fL
Frequency Capture
Range 2 fC
Loop Filter
Component
Selection
TL F 5968–7
TL F 5968 – 8
TL F 5968 – 9
TL F 5968 – 10
VCO in PLL system will adjust
VCO in PLL system will adjust to
to center frequency fo
lowest operating frequency fmin
2 fL e full VCO frequency range
2 fL e fmax b fmin
TL F 5968–11
02 fC
1 2 q fL
q u1
For 2 fC see Ref
fC e fL
TL F 5968–12
Phase Angle Between
Single and Comparator
Locks on Harmonics
of Center Frequency
Signal Input Noise
Rejection
90 at center frequency (fo) approximating
0 and 180 at ends of lock range (2 fL)
Yes
High
Always 0 in lock
No
Low
VCO Component
Selection
Given fo
Use fo with
Figure 5a to
determine R1
and C1
Given fo and fL
Calculate fmin
from the equation
fmin e fo b fL
Use fmin with Figure 5b
to determine R2 and C1
Calculate fmax
fmin
from the equation
fmax e fo a fL
fmin fo b fL
Use fmax with Figure 5c
fmin
to determine ratio R2
R1 to obtain R1
Given fmax
Calculate fo from
the equation
fo
e
fmax
2
Use fo with Figure 5a to
determine R1 and C1
Given fmin and fmax
Use fmin with
Figure 5b to
determine R2 and C1
Calculate fmax
fmin
Use fmax with Figure 5c
fmin
to determine ratio
R2 R1 to obtain R1
References
G S Moschytz ‘‘Miniaturized RC Filters Using Phase-Locked Loop’’ BSTJ May 1965
Floyd Gardner ‘‘Phaselock Techniques’’ John Wiley Sons 1966
11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet CD4046BC.PDF ] | |
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