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HI-8454 PDF даташит

Спецификация HI-8454 изготовлена ​​​​«HOLTIC» и имеет функцию, называемую «Single / Quad ARINC 429 Line Receivers».

Детали детали

Номер произв HI-8454
Описание Single / Quad ARINC 429 Line Receivers
Производители HOLTIC
логотип HOLTIC логотип 

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HI-8454 Даташит, Описание, Даташиты
December 2016
HI-8450, HI-8451, HI-8454, HI-8455
Single / Quad ARINC 429 Line Receivers with
Integrated DO-160G Level 3 Lightning Protection
GENERAL DESCRIPTION
Holt’s family of ARINC 429 line receivers include internal
lightning protection circuitry which ensures compliance
with RTCA/DO-160G, Section 22 Level 3 Pin Injection
Test Waveform Set A (3 & 4), Set B (3 & 5A) and Set Z (3
& 5B) without the use of any external components. Pin
surge levels for Level 3 are summarized below. The HI-
8450 and HI-8451 are single ARINC 429 line receivers
available in compact 8-pin SOIC packages. The HI-8454
and HI-8455 contain 4 independent ARINC 429 line
receivers.
Waveform
3
VOC/ISC
600V/24A
Waveform
4
VOC/ISC
300V/60A
Waveform
5A
VOC/ISC
300V/300A
Waveform
5B
VOC/ISC
300V/300A
The devices are designed to operate from either a 5V or
3.3V supply. Each receiver channel translates incoming
ARINC 429 data bus signals to a pair of TTL / CMOS
outputs.
The TESTA and TESTB inputs bypass the analog inputs
for testing purposes. They force the receiver outputs to
the specified ZERO, ONE or NULL state. The ARINC
inputs are ignored when the devices are in test mode.
The HI-8451 and HI-8454 produce low outputs when
the TESTA and TESTB inputs are held high, whereas
the HI-8450 produces high impedance outputs when
the TESTA and TESTB inputs are held high. The HI-
8455 does not have TEST inputs and these pins may be
considered no-connect (NC).
The parts are available in Industrial -40oC to +85oC, or
Extended, -55oC to +125oC temperature ranges. Optional
burn-in is available on the extended temperature range.
FEATURES
Internal lightning protection circuitry ensures
compliance with RTCA/DO-160G, Section 22
Level 3 Pin Injection Test Waveform Set A (3 &
4), Set B (3 & 5A) and Set Z (3 & 5B)
Direct connection to ARINC 429 bus with no
external components
3.3V or 5.0V single supply operation
Test inputs bypass analog inputs and force digital
outputs to a one, zero, or null state (not available
on HI-8455)
Industrial and Extended temperature ranges
Burn-in available
PIN CONFIGURATION (TOP VIEW)
VDD 1
8 TESTB
TESTA 2 HI-8450PSx 7 OUTB
INB 3 HI-8451PSx 6 OUTA
INA 4
5 GND
8-PIN PLASTIC SOIC - NB
IN1A 1
IN1B 2
IN2A 3
IN2B 4
TESTA (8454 only) 5
TESTB (8454 only) 6
IN3A 7
IN3B 8
IN4A 9
IN4B 10
HI-8454PSx
&
HI-8455PSx
Quad
Receiver
20 OUT1A
19 OUT1B
18 OUT2A
17 OUT2B
16 VDD
15 GND
14 OUT3A
13 OUT3B
12 OUT4A
11 OUT4B
20-PIN PLASTIC TSSOP PACKAGE
Table 1.  Function Table
ARINC
INPUTS
INA - INB
-2.5 to +2.5V
< -6.5V
> +6.5V
x
TESTA
0
0
0
0
TESTB
0
0
0
1
OUTA
0
0
1
0
x 101
x 1 1 0 (1)
x 1 1 HI-Z (2)
Note (1): HI-8451 and HI-8454 only.
Note (2): HI-8450 only.
OUTB
0
1
0
1
0
0 (1)
HI-Z (2)
DS8450 Rev. A
HOLT INTEGRATED CIRCUITS
www.holtic.com
1
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HI-8454 Даташит, Описание, Даташиты
HI-8450, HI-8451, HI-8454, HI-8455
FUNCTIONAL DESCRIPTION
Figure 1 shows the general architecture of an ARINC 429
receiver. The receiver operates off the VDD supply only.
The inputs RINA and RINB may be connected directly to
the ARINC 429 bus. Internal lightning protection circuitry
ensures compliance with RTCA/DO-160G, Section 22
Level 3 Pin Injection Test Waveform Set A (3 & 4), Set
B (3 & 5A) and Set Z (3 & 5B) without the use of any
external components.
After level translation, the inputs are buffered and
become inputs to a differential amplifier. The amplitude
of the differential signal is compared to levels derived
from a divider between VDD and Ground. The nominal
settings correspond to a One/Zero amplitude of 6.0V
and a Null amplitude of 3.3V.
The status of the ARINC receiver input is latched. A Null
input resets the latches and a One or Zero input sets the
latches.
The logic at the output is controlled by the test signal
which is generated by the logical OR of the TESTA and
TESTB pins (not available on HI-8455). If TESTA and
TESTB are both One, the outputs are pulled low (HI-
8451 and HI-8454 only). This allows the digital outputs
of a transmitter to be connected to the test inputs
through control logic for system self-test purposes. In
the case of HI-8450, if TESTA and TESTB are both One,
the outputs are high impedance (HI-Z).
BLOCK DIAGRAMS
RINA
RINB
LIGHTNING
PROTECTION
AND
TRANSLATION
ONE
NULL
ZERO
NULL
SQ
LATCH
R
TEST
TESTA
TESTB
SQ
LATCH
R
TEST
TESTA
TESTB
ROUTA
ROUTB
Figure 1.  Line Receiver Block Diagram
IN1A
IN1B
IN2A
IN2B
IN3A
IN3B
IN4A
IN4B
TESTA
TESTB
OUT1A
OUT1B
OUT2A
OUT2B
OUT3A
OUT3B
OUT4A
OUT4B
Figure 2.  HI-8454 Block Diagram
HOLT INTEGRATED CIRCUITS
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HI-8454 Даташит, Описание, Даташиты
HI-8450, HI-8451, HI-8454, HI-8455
PIN DESCRIPTIONS
Symbol
IN1A
IN1B
IN2A
IN2B
TESTA
TESTB
IN3A
IN3B
IN4A
IN4B
OUT4B
OUT4A
OUT3B
OUT3A
GND
VDD
OUT2B
OUT2A
OUT1B
OUT1A
Table 2.  Pin Descriptions
Function
Description
ARINC INPUT Receiver 1 positive input
ARINC INPUT Receiver 1 negative input
ARINC INPUT Receiver 2 positive input
ARINC INPUT Receiver 2 negative input
LOGIC INPUT Test input (not available on HI-8455)
LOGIC INPUT Test input (not available on HI-8455)
ARINC INPUT Receiver 3 positive input
ARINC INPUT Receiver 3 negative input
ARINC INPUT Receiver 4 positive input
ARINC INPUT Receiver 4 negative input
LOGIC OUTPUT Receiver 4 “ZERO” output
LOGIC OUTPUT Receiver 4 “ONE” output
LOGIC OUTPUT Receiver 3 “ZERO” output
LOGIC OUTPUT Receiver 3 “ONE” output
POWER
Ground supply voltage
POWER
+3.3V or +5V supply voltage
LOGIC OUTPUT Receiver 2 “ZERO” output
LOGIC OUTPUT Receiver 2 “ONE” output
LOGIC OUTPUT Receiver 1 “ZERO” output
LOGIC OUTPUT Receiver 1 “ONE” output
HOLT INTEGRATED CIRCUITS
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Номер в каталогеОписаниеПроизводители
HI-8450Single / Quad ARINC 429 Line ReceiversHOLTIC
HOLTIC
HI-8451Single / Quad ARINC 429 Line ReceiversHOLTIC
HOLTIC
HI-8454Single / Quad ARINC 429 Line ReceiversHOLTIC
HOLTIC
HI-8455Single / Quad ARINC 429 Line ReceiversHOLTIC
HOLTIC

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