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PDF NT6862 Data sheet ( Hoja de datos )
| Número de pieza | NT6862 | |
| Descripción | 8-Bit Microcontroller | |
| Fabricantes | Novatek | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de NT6862 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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NT6862-5xxxx
8-Bit Microcontroller for Monitor
Features
n Operating voltage range: 4.5V to 5.5V
n CMOS technology for low power consumption
n 6502 8-bit CMOS CPU core
n 8 MHz operation frequency
n 32K/24K/16K bytes of ROM
n 512 bytes of RAM
n One 8-bit base timer
n 13 channels of 8-bit PWM outputs with 5V open drain
n 4 channel A/D converters with 6-bit resolution
n 25 bi-directional I/O port pins (8 dedicated I/O pins)
n Hsync/Vsync signals processor for separate &
composite signals which includes hardware sync
signals polarity detection and frequency counters with
2 sets of Hsync counting intervals
n Hsync/Vsync polarity controlled output, 5 selectable
free run output signals and self-test patterns, auto-
mute function, half freq. I/O function
n Add a jitter filter at the front end of Hsync input path,
reduce the jitter interference of Hysync input
n Two built-in I2C bus interfaces support VESA
DDC1/2B+
n Two layers of interrupt management
NMI interrupt sources
- INTE0 (External INT with selectable edge trigger)
- INTMUTE (Auto Mute Activated)
IRQ interrupt sources
- INTS0/1 (SCL Go-low INT)
- INTA0/1 (Slave Address Matched INT)
- INTTX0/1 (Shift Register INT)
- INTRX0/1 (Shift Register INT)
- INTNAK0/1 (No Acknowledge)
- INTSTOP0/1 (Stop Condition Occurred INT)
- INTE1 (External INT with Selectable Edge Trigger)
- INTV (VSYNC INT)
- INTMR (Base Timer INT)
- INTADC (AD Conversion Done INT)
n Hardware Watch-dog timer function
n 40-pin P-DIP and 42-pin S-DIP packages
General Description
The NT6862 is a new generation monitor µC for auto-sync
and digital control applications. Particularly, this chip
supports various and efficient functions to allow users to
easily develop USB monitors. It contains the 6502 8-bit
CPU core, 512 bytes of RAM used as working RAM and
stack area, 32K bytes of OTP ROM, 13-channels of 8-bit
PWM D/A converters, 4-channel A/D converters for key
detection which save I/O pins, one 8-bit pre-loadable base
timer, internal Hsync and Vsync signals processor, a
Watch-dog timer which prevents the system from abnormal
operation, and two I2C bus interfaces. The user can store
EDID data in the 128 bytes of RAM for DDC1/2B, so that
user can reduce a dedicated EEPROM for EDID. A Half
frequency output function can save external one-shot
circuit. These designs are committed to reduce component
cost. The 42 pin S-DIP IC provides two additional I/O pins –
port40 & port41, Part number NT6862U represents the S-
DIP IC. For future reference, port40 & port42 are only
available for the 42 pin S-DIP IC.
1 V2.2
1 page  
NT6862-5xxxx
Pin Description (continued)
Pin No.
40 Pin 42 Pin
36 38
37 39
38 40
39 41
40 42
-6
- 37
Designation Reset Init.
DAC5/SDA1
[ MODE2 ]
DAC4/SCL1
[ MODE1 ]
DAC3
[ MODE0 ]
HSYNCI
VSYNCI/INTV VSYNCI
[ A14 ]
P40
P41
I/O Description
O Open drain 5V, D/A converter output 5, shared with open
drain SDA1 line of I2C bus, Schmitt Trigger buffer
[ I ] [ OTP ROM mode select ]
O Open drain 5V, D/A converter output 4, shared with open
drain SCL1 line of I2C bus, Schmitt Trigger buffer
[ I ] [ OTP ROM mode select ]
O Open drain 5V, D/A converter output 3
[ I ] [ OTP ROM mode select ]
I Debouncing & Schmitt Trigger input pin for video
horizontal sync signal internally pulled high, shared with
composite sync input. A jitter filter is added at the front
end, it could effectually reduce the jitter interference of
external noisy Hsync input.
I Debouncing & Schmitt Trigger input pin for video vertical
sync signal, internal pull high, shared with input pin of
external interrupt source intv with Schmitt Trigger,
selectable triggered, and internal pulled up 22KΩ register
[ I ] [ OTP ROM program address buffer ]
I/O Bi-directional I/O pin with internal pulled up 22KΩ
register, only 42 pin S-DIP available
I/O Bi-directional I/O pin with internal pulled up 22KΩ
register, only 42 pin S-DIP available
* This RESET pin must be pulled high by an external pulled-up register (5KΩ suggestion), or it will remain in low voltage
and continually keep the system in a rest state..
5
5 Page 
NT6862-5xxxx
System Registers (continued)
Addr.
$0016
$0017
$0018
$0019
$001A
$001B
$001C
$001D
$001E
$001F
$0020
$0021
$0022
$0023
$0024
$0025
$0026
$0027
$0028
Register INIT Bit7
Bit6
Bit5 Bit4
Bit3
Bit2
Bit1
Bit0
Control Register for Polling (Read) Interrupt Groups & Clearing (Write) INTE0 & INTMUTE Interrupt Requests
NMIPOLL 00H
-
-
-
-
-
-
INTE0
INTMUTE
- - - - - - CLRE0 CLRMUTE
IRQPOLL 00H
-
-
-
-
-
IRQ2
IRQ1
IRQ0
Control Registers of Interrupt Enable
IENMI
00H
-
-
-
-
-
-
INTE0
INTMUTE
IEIRQ0
00H
-
-
INTS0
INTA0 INTTX0 INTRX0 INTNAK0 INTSTOP0
IEIRQ1
00H
-
-
INTS1
INTA1 INTTX1 INTRX1 INTNAK1 INTSTOP1
IEIRQ2
00H
-
-
-
-
INTADC
INTV
INTE1
INTMR
Control Registers for Polling (Read) & Clearing (Write) Interrupt Requests
IRQ0 00H -
-
INTS0
INTA0 INTTX0 INTRX0 INTNAK0 INTSTOP0
- - CLRS0 CLRA0 CLRTX0 CLRRX0 CLRNAK0 CLRSTOP0
IRQ1 00H -
-
INTS1
INTA1 INTTX1 INTRX1 INTNAK1 INTSTOP1
- - CLRS1 CLRA1 CLRTX1 CLRRX1 CLRNAK1 CLRSTOP1
IRQ2 00H -
-
-
-
INTADC
INTV
INTE1
INTMR
-
-
-
-
CLRADC CLRV
CLRE1
CLRMR
Selection of Edge Triggered for INTV, INTE0 & 1 Interrupts
TRIGGER FFH
-
-
-
-
- INTVR INTE1R INTE0R
Control Registers for Clearing Watch Dog Timer
CLR WDT
-
0
1
01
0
1
0
1
Control Register for DDC1/2B+ of Channel 0
CH0ADDR A0H ADR7
ADR6
ADR5
ADR4
ADR3
ADR2
ADR1
-
CH0TXDAT 00H
TX7
TX6
TX5 TX4
TX3
TX2
TX1
TX0
CH0RXDAT 00H
RX7
RX6
RX5 RX4
RX3
RX2
RX1
RX0
CH0CON E0H ENDDC MD1/ 2
-
START
STOP
-
TXACK
-
-
-
SRW
START
STOP
-
-
-
CH0CLK
FFH MODE
MRW RSTART
-
- DDC2BR2 DDC2BR1 DDC2BR0
Control Register for DDC1/2B+ of Channel 1
CH1ADDR A0H ADR7
ADR6
ADR5
ADR4
ADR3
ADR2
ADR1
-
CH1TXDAT 00H
TX7
TX6
TX5 TX4
TX3
TX2
TX1
TX0
CH1RXDAT 00H
RX7
RX6
RX5 RX4
RX3
RX2
RX1
RX0
R/W
R
W
R
RW
RW
RW
RW
R
W
R
W
R
W
R/W
W
W
W
R
W
R
W
W
W
R
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet NT6862.PDF ] | |
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