CD4099BC PDF даташит
Спецификация CD4099BC изготовлена «Fairchild Semiconductor» и имеет функцию, называемую «8-Bit Addressable Latch». |
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Детали детали
Номер произв | CD4099BC |
Описание | 8-Bit Addressable Latch |
Производители | Fairchild Semiconductor |
логотип |
6 Pages
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October 1987
Revised January 1999
CD4099BC
8-Bit Addressable Latch
General Description
The CD4099BC is an 8-bit addressable latch with three
address inputs (A0–A2), an active low enable input (E),
active high clear input (CL), a data input (D), and eight out-
puts (Q0–Q7).
Data is entered into a particular bit in the latch when that bit
is addressed by the address inputs and the enable (E) is
LOW. Data entry is inhibited when enable (E) is HIGH.
When clear (CL) and enable (E) are HIGH, all outputs are
LOW. When clear (CL) is HIGH and enable (E) is LOW, the
channel demultiplexing occurs. The bit that is addressed
has an active output which follows the data input while all
unaddressed bits are held LOW. When operating in the
addressable latch mode (E = CL = LOW), changing more
than one bit of the address could impose a transient wrong
address. Therefore, this should only be done while in the
memory mode (E = HIGH, CL = LOW).
Features
s Wide supply voltage range: 3.0V to 15V
s High noise immunity: 0.45 VDD (typ.)
s Low power TTL: fan out of 2 driving 74L
compatibility: or 1 driving 74LS
s Serial to parallel capability
s Storage register capability
s Random (addressable) data entry
s Active high demultiplexing capability
s Common active high clear
Ordering Code:
Order Number Package Number
Package Description
CD4099BCN
N16E
16-Lead Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Connection Diagram
Pin Assignments for DIP
Truth Table
Top View
Mode Selection
E CL
Addressed
Unaddressed
Mode
Latch
Latch
L L Follows Data
Holds Previous Data Addressable Latch
H L Holds Previous Data Holds Previous Data Memory
L H Follows Data
Reset to “0”
Demultiplexer
H H Reset to “0”
Reset to “0”
Clear
© 1999 Fairchild Semiconductor Corporation DS005984.prf
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Logic Diagram
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Absolute Maximum Ratings(Note 1)
(Note 2)
DC Supply Voltage (VDD)
Input Voltage (VIN)
Storage Temperature
Range (TS)
Power Dissipation (PD)
Dual-In-Line
Small Outline
Lead Temperature (TL)
(Soldering, 10 seconds)
−0.5 to +18 VDC
−0.5 to VDD +0.5 VDC
−65°C to +150°C
700 mW
500 mW
260°C
Recommended Operating
Conditions (Note 2)
DC Supply Voltage (VDD)
3.0 to 15 VDC
Input Voltage (VIN)
0 to VDD VDC
Operating Temperature Range (TA)
−40°C to +85°C
Note 1: “Absolute Maximum Ratings” are those values beyond which the
safety of the device cannot be guaranteed; they are not meant to imply that
the devices should be operated at these limits. The tables of “Recom-
mended Operating Conditions” and “Electrical Characteristics” provide con-
ditions for actual device operation.
Note 2: VSS = 0V unless otherwise specified.
DC Electrical Characteristics (Note 2)
Symbol
Parameter
Conditions
IDD Quiescent Device
VDD = 5V, VIN = VDD or VSS
Current
VDD = 10V, VIN = VDD or VSS
VDD = 15V, VIN = VDD or VSS
VOL LOW Level
|IO| ≤ 1µA
Output Voltage
VDD = 5V
VDD = 10V
VDD = 15V
VOH HIGH Level
|IO| ≤ 1 µA
Output Voltage
VDD = 5V
VDD = 10V
VDD = 15V
VIL LOW Level
VDD = 5V, VO = 0.5V or 4.5V
Input Voltage
VDD = 10V, VO = 1.0V or 9.0V
VDD = 15V, VO = 1.5V or 13.5V
VIH HIGH Level
VDD = 5V, VO = 0.5V or 4.5V
Input Voltage
VDD = 10V, VO = 1.0V or 9.0V
VDD = 15V, VO = 1.5V or 13.5V
IOL LOW Level Output
VDD = 5V, VO = 0.4V
Current (Note 3)
VDD = 10V, VO = 0.5V
VDD = 15V, VO = 1.5V
IOH HIGH Level Output
VDD = 5V, VO = 4.6V
Current (Note 3)
VDD = 10V, VO = 9.5V
VDD = 15V, VO = 13.5V
IIN Input Current
VDD = 15V, VIN = 0V
VDD = 15V, VIN = 15V
Note 3: IOH and IOL are tested one output at a time.
−40°C
Min Max
20
40
80
+25°C
Min Typ Max
0.02 20
0.02 40
0.02 80
+85°C
Min Max
150
300
600
Units
µA
µA
µA
0.05
0.05
0.05
0 0.05
0 0.05
0 0.05
0.05
0.05
0.05
V
V
V
4.95
9.95
14.95
3.5
7.0
11.0
0.52
1.3
3.6
−0.52
−1.3
−3.6
1.5
3.0
4.0
−0.30
0.30
4.95
9.95
14.95
3.5
7.0
11.0
0.44
1.1
3.0
−0.44
−1.1
−3.0
5
10
15
2.25
4.5
6.75
2.75
5.5
8.25
0.88
2.25
8.8
−0.88
−2.25
−8.8
−10−5
10−5
1.5
3.0
4.0
−0.30
0.30
4.95
9.95
14.95
3.5
7.0
11.0
0.36
0.9
2.4
−0.36
−0.9
−2.4
1.5
3.0
4.0
−1.0
1.0
V
V
V
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
µA
µA
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