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PDF CD4511BMS Data sheet ( Hoja de datos )
| Número de pieza | CD4511BMS | |
| Descripción | CMOS BCD-to-7-Segment Latch Decoder Drivers | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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CD4511BMS
December 1992
CMOS BCD-to-7-Segment
Latch Decoder Drivers
Features
Pinout
• High Voltage Type (20V Rating)
• High Output Sourcing Capability up to 25mA
CD4511BMS
TOP VIEW
• Input Latches for BCD Code Storage
• Lamp Test and Blanking Capability
• 7 Segment Outputs Blanked for BCD Input Codes
> 1001
• 100% Tested for Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25oC
Applications
B1
C2
LT 3
BL 4
LE/STROBE 5
D6
A7
VSS 8
16 VDD
15 f
14 g
13 a
12 b
11 c
10 d
9e
• Driving Common Cathode LED Displays
• Multiplexing with Common Cathode LED Displays
• Driving Incandescent Displays
Functional Diagram
• Driving Low Voltage Fluorescent Displays
Description
CD4511BMS is a BCD-to-7-Segment latch decoder drivers
constructed with CMOS logic and n-p-n bipolar transistor
output devices on a single monolithic structure. These
devices combine the low quiescent power dissipation and
high noise immunity features of Intersil CMOS with n-p-n
bipolar output transistors capable of sourcing up to 25mA.
This capability allows the CD4511BMS types to drive LED’s
and other displays directly.
Lamp Test (LT), Blanking (BL), and Latch Enable or Strobe
inputs are provided to test the display, shut off or intensity
modulate it, and store or strobe a BCD code, respectively.
Several different signals may be multiplexed and displayed
when external multiplexing circuitry is used.
7
A
BCD
INPUTS
1
B
2
C
6
D
L
A
T
C
H
5
LE/STROBE
VSS = 8
VDD = 16
LT
3
D
E
C
O
D
E
R
4
BL
13 a
12 b
D 11 c
R7
I
V
E
R
10 d
9e
SEGMENT
OUTPUTS
15 f
14 g
These devices are similar to the type MC14511.
The CD4511BMS is supplied in these 16-lead outline
packages:
7-Segment Display
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4W
H2R
H6W
a
f gb
ec
d
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-1169
File Number 3339
1 page  
Specifications CD4511BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS(Continued)
LIMITS
PARAMETER
Output Drive Voltage
SYMBOL
CONDITIONS
LVOH15 VDD = 15V, IOH = -10mA
Input Capacitance
VDD = 15V, IOH = -20mA
VDD = 15V, IOH = -25mA
CIN Any Input
NOTES
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
TEMPERATURE
+25oC
+125oC
-55oC
+125oC
-55oC
+25oC
-55oC
+25oC
MIN
14.0
14.0
13.9
13.5
13.75
13.5
13.65
-
MAX
-
-
-
-
-
-
-
7.5
UNITS
V
V
V
V
V
V
V
pF
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
N Threshold Voltage
N Threshold Voltage
Delta
P Threshold Voltage
P Threshold Voltage
Delta
Functional
Propagation Delay Time
SYMBOL
CONDITIONS
IDD VDD = 20V, VIN = VDD or GND
VNTH VDD = 10V, ISS = -10µA
∆VTN VDD = 10V, ISS = -10µA
VTP
∆VTP
VSS = 0V, IDD = 10µA
VSS = 0V, IDD = 10µA
F
TPHL
TPLH
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
VDD = 5V
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
NOTES
1, 4
1, 4
1, 4
TEMPERATURE
+25oC
+25oC
+25oC
MIN
-
-2.8
-
1, 4
+25oC
0.2
1, 4
+25oC
-
1
1, 2, 3, 4
+25oC
+25oC
VOH >
VDD/2
-
3. See Table 2 for +25oC limit.
4. Read and Record
MAX
25
-0.2
±1
2.8
±1
VOL <
VDD/2
1.35 x
+25oC
Limit
UNITS
µA
V
V
V
V
V
ns
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC
PARAMETER
SYMBOL
DELTA LIMIT
Supply Current - MSI-2
Output Current (Sink)
Output Current (Source)
IDD
IOL5
IOH5A
± 1.0µA
± 20% x Pre-Test Reading
± 20% x Pre-Test Reading
CONFORMANCE GROUP
Initial Test (Pre Burn-In)
Interim Test 1 (Post Burn-In)
Interim Test 2 (Post Burn-In)
TABLE 6. APPLICABLE SUBGROUPS
MIL-STD-883
METHOD
GROUP A SUBGROUPS
100% 5004
1, 7, 9
100% 5004
1, 7, 9
100% 5004
1, 7, 9
READ AND RECORD
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
7-1173
5 Page 
CD4511BMS
Applications Interfacing with Various Displays (Continued)
MULTIPLEXING SCHEME SHOWING
2 OF 7 SEGMENTS CONNECTED
TRANSISTORS T1 - T4 (2N3053 OR 2N2102)
HAVE IC MAX. RATING > 7 x ISEG
DUTY CYCLE = 25%
ISEG = (IDIODEAVG) x 4
(VOH - VDF-VCE)
R=
ISEG
LT
A
B
C
D
LE
VDD
BL
VSS
VDD
aR
b
c
d
e
f
gR
+
-
VOH
ISEG
+
VDF
-
VO1 12 2
Q0 4
1 V02 11
CD4024BMS
2 VO3 9
3 Q1 5
CD4555BMS
1 Q2 6
VSS
Q3 7
+
VCE
T1 -
VSS
T2
VSS
T3
VSS
T4
VSS
FIGURE 12. MULTIPLEXING WITH COMMON CATHODE 7-SEGMENT LED DISPLAYS (EXAMPLE HEWLET-PACKARD 5082-7404
4 CHARACTER DISPLAY OR 4 DISCRETE MONOSANTO MAN 3 DISPLAYS)
Waveforms
tr
DATA
INPUT
tTHL
OUTPUT
tPHL
tr, tf = 20ns
tf
tTLH
tPLH
90%
50%
10%
VDD
0
90%
50%
10%
VDD
0
20ns
LE
DATA
50%
INPUTS 10%
20ns
10%
tSU
90%
90%
50%
tHOLD
VDD
0
VDD
50%
0
FOR SETUP
VDD
OUTPUT
20ns
STROBE
90%
50%
tr, tf = 20ns 10%
tW
FOR HOLD
0
20ns
FIGURE 13. DYNAMIC WAVEFORMS
Chip Dimensions and Pad Layout
Dimensions in parenthesis are in millimeters and are
derived from the basic inch dimensions as indicated.
Grid graduations are in mils (10-3 inch).
METALLIZATION: Thickness: 11kÅ − 14kÅ, AL.
PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches
7-1179
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet CD4511BMS.PDF ] | |
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