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PDF CD4517BMS Data sheet ( Hoja de datos )
| Número de pieza | CD4517BMS | |
| Descripción | CMOS Dual 64-Stage Static Shift Register | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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CD4517BMS
December 1992
CMOS Dual 64-Stage
Static Shift Register
Features
Description
• High-Voltage Types (20-Volt Rating)
• Low Quiescent Current - 10nA/pkg (Typ.) at VDD = 5V
• Clock Frequency 12MHz (Typ.) at VDD = 10V
• Schmitt Trigger Clock Inputs Allow Operation with Very Slow Clock
Rise and Fall Times
• Capable of Driving Two Low-power TTL Loads, One Low-power
Schottky TTL Load, or Two HTL Loads
• 3-State Outputs
• 100% Tested for Quiescent Current at 20V
• Standardized, Symmetrical Output Characteristics
• 5V, 10V, and 15V Parametric Ratings
• Meets all Requirements of JEDEC Tentative Standard No. 13B,
"Standard Specifications for Description of ‘B’ Series CMOS
Devices"
Applications
• Time-delay Circuits
CD4517BMS dual 64-stage static shift
register consists of two independent registers
each having a clock, data, and write enable
input and outputs accessible at taps following
the 16th, 32rd, 48th, and 64th stages. These
taps also serve as input points allowing data
to be inputted at the 17th, 33rd, and 49th
stages when the write enable input is a logic
1 and the clock goes through a low-to-high
transition. The truth table indicates how the
clock and write enable inputs control the
opeation of the CD4517BMS. Inputs at the
intermediate taps allow entry of 64 bits into
the register with 16 clock pulses. The 3-state
outputs permit connection of this device to an
external bus.
The CD4517BMS is supplied in these 16 lead
outline packages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4X
H1F
H6P
• Scratch-pad Memories
• General-purpose Serial Shift-register Applications
Pinout
CD4517BMS
TOP VIEW
Q16A 1
Q48A 2
WEA 3
CLA 4
Q64A 5
Q32A 6
DA 7
VSS 8
16 VDD
15 Q16B
14 Q48B
13 WEB
12 CLB
11 Q64B
10 Q32B
9 DB
Functional Diagram
CL
CL
Q16
D D1
16 STAGES
CL
Q32
D17
16 STAGES
WE = 0
WE = 1
WE
CL
Q48
D33
16 STAGES
CL
Q64
D49
16 STAGES
STAGE 16
OUT/IN TAP
STAGE32
OUT/IN TAP
STAGE 48
OUT/IN TAP
STAGE 64
OUT/IN TAP
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-1197
File Number 3341
1 page  
Specifications CD4517BMS
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
PARAMETER
P Threshold Voltage
Delta
Functional
Propagation Delay Time
SYMBOL
CONDITIONS
∆VTP VSS = 0V, IDD = 10µA
F
TPHL
TPLH
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
VDD = 5V
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
NOTES
1, 4
TEMPERATURE
+25oC
MIN
-
1
1, 2, 3, 4
+25oC
+25oC
VOH >
VDD/2
-
3. See Table 2 for +25oC limit.
4. Read and Record
MAX
±1
VOL <
VDD/2
1.35 x
+25oC
Limit
UNITS
V
V
ns
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC
PARAMETER
SYMBOL
DELTA LIMIT
Supply Current - MSI-2
Output Current (Sink)
Output Current (Source)
IDD
IOL5
IOH5A
± 1.0µA
± 20% x Pre-Test Reading
± 20% x Pre-Test Reading
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUP
MIL-STD-883
METHOD
GROUP A SUBGROUPS
Initial Test (Pre Burn-In)
100% 5004
1, 7, 9
Interim Test 1 (Post Burn-In)
100% 5004
1, 7, 9
Interim Test 2 (Post Burn-In)
100% 5004
1, 7, 9
PDA (Note 1)
100% 5004
1, 7, 9, Deltas
Interim Test 3 (Post Burn-In)
100% 5004
1, 7, 9
PDA (Note 1)
100% 5004
1, 7, 9, Deltas
Final Test
100% 5004
2, 3, 8A, 8B, 10, 11
Group A
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group B
Subgroup B-5
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Subgroup B-6
Sample 5005
1, 7, 9
Group D
Sample 5005
1, 2, 3, 8A, 8B, 9
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
READ AND RECORD
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
CONFORMANCE GROUPS
Group E Subgroup 2
TABLE 7. TOTAL DOSE IRRADIATION
MIL-STD-883
METHOD
TEST
PRE-IRRAD
POST-IRRAD
5005
1, 7, 9
Table 4
READ AND RECORD
PRE-IRRAD
POST-IRRAD
1, 9 Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
OPEN
GROUND
VDD
9V ± -0.5V
50kHz
25kHz
Static Burn-In 1 1, 2, 5, 6, 10, 11, 3, 4, 7-9, 12, 13
(Note 1)
14, 15
16
Static Burn-In 2 1, 2, 5, 6, 10, 11, 8 3, 4, 7, 9, 12, 13,
(Note 1)
14, 15
16
Dynamic Burn-
In (Note 1)
-
3, 8, 13
16
1, 2, 5, 6, 10, 11,
4, 12
14, 15
7, 9
7-1201
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet CD4517BMS.PDF ] | |
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