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PDF CD4536BMS Data sheet ( Hoja de datos )
| Número de pieza | CD4536BMS | |
| Descripción | CMOS Programmable Timer | |
| Fabricantes | Intersil Corporation | |
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CD4536BMS
December 1992
CMOS Programmable Timer
Features
Description
• High Voltage Type (20V Rating)
• 24 Flip-Flop Stage - Counts from 20 to 224
• Last 16 Stages Selectable by BCD Select Code
• Bypass Input Allows Bypassing First 8 Stages
• On-Chip RC Oscillator Provision
• Clock Inhibit Input
• Schmitt Trigger in clock Line Permits Operation with
Very Long Rise and Fall Times
• On-Chip Monostable Output Provision
• Typical fCL = 3MHz at VDD = 10V
• Test Mode Allows Fast Test Sequence
• Set and Reset Inputs
• Capable of Driving Two Low Power TTL Loads, One
Lower Power Schottky Load, or Two HTL Loads Over
the Rated Temperature Range
• 100% Tested for Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
• Standardized, Symmetrical Output Characteristics
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
CD4536BMS is a programmable timer consisting of 24 ripple
binary counter stages. The salient feature of this device is its
flexibility. The device can count from 1 to 224 or the first 8
stages can be bypassed to allow an output, selectable by a
4-bit code, from any one of the remaining 16 stages. It can
be driven by an external clock or an RC oscillator that can be
constructed using on-chip components. Input IN1 serves as
either the external clock input or the input to the on-chip RC
oscillator. OUT1 and OUT2 are connection terminals for the
external RC components. In addition, an on-chip monostable
circuit is provided to allow a variable pulse width output. Var-
ious timing functions can be achieved using combinations of
these capabilities.
A logic 1 on the 8-BYPASS input enables a bypass of the
first 8 stages and makes stage 9 the first counter stage of
the last 16 stages. Selection of 1 of 16 outputs is accom-
plished by the decoder and the BCD inputs A, B, C and D.
MONO IN is the timing input for the on-chip monostable
oscillator. Grounding of the MONO IN terminal through a
resistor of 10kΩ or higher, disables the one-shot circuit and
connects the decoder directly to the DECODE OUT terminal.
A resistor to VDD and a capacitor to ground from the MONO
IN terminal enables the one-shot circuit and controls its
pulse width.
A fast test mode is enabled by a logic 1 on 8-BYPASS, SET,
and RESET. This mode divides the 24-stage counter into
three 8-stage sections to facilitate a fast test sequence.
The CD4536BMS is supplied in these 16-lead outline packages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4X
H1F
H6W
Pinout
CD4536BMS
TOP VIEW
SET 1
RESET 2
IN 1 3
OUT 1 4
OUT 2 5
8-BYPASS 6
CLOCK INHIBIT 7
VSS 8
16 VDD
15 MONO IN
14 OSC INHIBIT
13 DECODE OUT
12 D
11 C
10 B
BINARY
SELECT
9A
Functional Diagram
8-BYPASS
6
CLOCK
INHIBIT
OSC
INHIBIT
IN 1
14 7 3
RS
9
A
BINARY
SELECT
10
B
11
C
12
D
1
SET
2
RESET
15
MONO IN
4
OUT 1
RT
5
OUT 2
13 DECODE
OUT
VSS = 8
VDD = 16
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-1236
File Number 3345
1 page  
Specifications CD4536BMS
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
N Threshold Voltage
N Threshold Voltage
Delta
P Threshold Voltage
P Threshold Voltage
Delta
Functional
Propagation Delay Time
SYMBOL
CONDITIONS
IDD VDD = 20V, VIN = VDD or GND
VNTH VDD = 10V, ISS = -10µA
∆VTN VDD = 10V, ISS = -10µA
VTP
∆VTP
VSS = 0V, IDD = 10µA
VSS = 0V, IDD = 10µA
F
TPHL
TPLH
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
VDD = 5V
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
NOTES
1, 4
1, 4
1, 4
TEMPERATURE
+25oC
+25oC
+25oC
MIN
-
-2.8
-
1, 4
+25oC
0.2
1, 4
+25oC
-
1
1, 2, 3, 4
+25oC
+25oC
VOH >
VDD/2
-
3. See Table 2 for +25oC limit.
4. Read and Record
MAX
25
-0.2
±1
2.8
±1
VOL <
VDD/2
1.35 x
+25oC
Limit
UNITS
µA
V
V
V
V
V
ns
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC
PARAMETER
SYMBOL
DELTA LIMIT
Supply Current - MSI-2
Output Current (Sink)
Output Current (Source)
IDD
IOL5
IOH5A
± 1.0µA
± 20% x Pre-Test Reading
± 20% x Pre-Test Reading
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUP
MIL-STD-883
METHOD
GROUP A SUBGROUPS
Initial Test (Pre Burn-In)
100% 5004
1, 7, 9
Interim Test 1 (Post Burn-In)
100% 5004
1, 7, 9
Interim Test 2 (Post Burn-In)
100% 5004
1, 7, 9
PDA (Note 1)
100% 5004
1, 7, 9, Deltas
Interim Test 3 (Post Burn-In)
100% 5004
1, 7, 9
PDA (Note 1)
100% 5004
1, 7, 9, Deltas
Final Test
100% 5004
2, 3, 8A, 8B, 10, 11
Group A
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group B
Subgroup B-5
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Subgroup B-6
Sample 5005
1, 7, 9
Group D
Sample 5005
1, 2, 3, 8A, 8B, 9
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
READ AND RECORD
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
CONFORMANCE GROUPS
Group E Subgroup 2
TABLE 7. TOTAL DOSE IRRADIATION
MIL-STD-883
METHOD
TEST
PRE-IRRAD
POST-IRRAD
5005
1, 7, 9
Table 4
READ AND RECORD
PRE-IRRAD
POST-IRRAD
1, 9 Table 4
7-1240
5 Page 
CD4536BMS
Typical Performance Characteristics (Continued)
105 8
6
AMBIENT TEMPERATURE (TA) = +25oC
4
2
104 8
6
4
SUPPLY VOLTAGE (VDD) = 15V
2
103 8
6
4
10V
5V
2
102 8
6
4
2
CL = 50pF
CL = 15pF
10
2
0.1
4 68 2 4 68 2 4 68 2
1 10 102
PULSE INPUT FREQUENCY (kHz)
4 68
103
FIGURE 18. TYPICAL DYNAMIC POWER DISSIPATION AS A FUNCTION OF INPUT PULSE FREQUENCY
Applications
>10K
VDD
9 16
10 A
B
11
OUT 1
C
12
D
1
SET
2
RESET
OUT 2
6
8-BYPASS
C INH
15
MONO IN
14
OSC INH
IN 1
DECODE
OUT
8
VSS
CX RX
VDD
12
4
+TR
5 -TR
3
R
12 +TR
11 -TR
13 R
15 14
16
Q1
8
R
CL
CODE OUT
(CL ÷ 8)
Q1 OUTPUT
CD4098BMS
FIGURE 19. APPLICATION SHOWING USE OF CD4098BMS AND CD4536BMS TO GET DECODE PULSE 8 CLOCK PULSES AFTER
RESET PULSE
CLOCK
VDD
A
B
C
D
SET
RESET
8-BYPASS
C INH
MONO IN
≥10kΩ
OSC INH
IN 1
DECODE
OUT
VSS
OUT 1
OUT 2
t
A
B
C
D
R
CL
CLOCK
VDD
OUT 1
SET
RESET
8-BYPASS
C INH
MONO IN
OSC INH
IN 1
DECODE
OUT
OUT 2
t
VSS
FIGURE 20. TIME INTERVAL CONFIGURATION USING EXTER-
NAL CLOCK; SET AND CLOCK INHIBIT FUNCTIONS
FIGURE 21. TIME INTERVAL CONFIGURATION USING EXTER-
NAL CLOCK; RESET AND OUTPUT MONOSTABLE
TO ACHIEVE A PULSE OUTPUT
7-1246
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet CD4536BMS.PDF ] | |
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