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CD4541BC PDF даташит

Спецификация CD4541BC изготовлена ​​​​«Fairchild Semiconductor» и имеет функцию, называемую «Programmable Timer».

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Номер произв CD4541BC
Описание Programmable Timer
Производители Fairchild Semiconductor
логотип Fairchild Semiconductor логотип 

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CD4541BC Даташит, Описание, Даташиты
October 1987
Revised March 1999
CD4541BC
Programmable Timer
General Description
The CD4541BC Programmable Timer is designed with a
16-stage binary counter, an integrated oscillator for use
with an external capacitor and two resistors, output control
logic, and a special power-on reset circuit. The special fea-
tures of the power-on reset circuit are first, no additional
static power consumption and second, the part functions
across the full voltage range (3V–15V) whether power-on
reset is enabled or disabled.
Timing and the counter are initialized by turning on power,
if the power-on reset is enabled. When the power is
already on, an external reset pulse will also initialize the
timing and counter. After either reset is accomplished, the
oscillator frequency is determined by the external RC net-
work. The 16-stage counter divides the oscillator frequency
by any of 4 digitally controlled division ratios.
Features
s Available division ratios 28, 210, 213, or 216
s Increments on positive edge clock transitions
s Built-in low power RC oscillator (±2% accuracy over
temperature range and ±10% supply and ±3% over pro-
cessing @ < 10 kHz)
s Oscillator frequency range DC to 100 kHz
s Oscillator may be bypassed if external clock is available
(apply external clock to pin 3)
s Automatic reset initializes all counters when power turns
on
s External master reset totally independent of automatic
reset operation
s Operates at 2n frequency divider or single transition
timer
s Q/Q select provides output logic level flexibility
s Reset (auto or master) disables oscillator during reset-
ting to provide no active power dissipation
s Clock conditioning circuit permits operation with very
slow clock rise and fall times
s Wide supply voltage range—3.0V to 15V
s High noise immunity—0.45 VDD (typ.)
s 5V–10V–15V parameter ratings
s Symmetrical output characteristics
s Maximum input leakage 1 µA at 15V over full tempera-
ture range
s High output drive (pin 8) min. one TTL load
Ordering Code:
Order Number Package Number
Package Description
CD4541BCN
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
CD4541BCM
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Assignments for DIP and SOIC
N.C.—Not connected
Top View
© 1999 Fairchild Semiconductor Corporation DS006001.prf
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CD4541BC Даташит, Описание, Даташиты
Truth Table
Pin State
01
5 Auto Reset Operating Auto Reset Disabled
6 Timer Operational
Master Reset On
9 Output Initially Low
Output Initially High
after Reset
after Reset
10 Single Cycle Mode
Recycle Mode
Division Ratio Table
Number of
A B Counter Stages
00
01
10
11
n
13
10
8
16
Count
2n
8192
1024
256
65536
Operating Characteristics
With Auto Reset pin set to a “0” the counter circuit is initial-
ized by turning on power. Or with power already on, the
counter circuit is reset when the Master Reset pin is set to
a “1”. Both types of reset will result in synchronously reset-
ting all counter stages independent of counter state.
The RC oscillator frequency is determined by the external
RC network, i.e.:
and RS 2 Rtc where RS 10 k
The time select inputs (A and B) provide a two-bit address
to output any one of four counter stages (28, 210, 213, and
216). The 2n counts as shown in the Division Ratio Table
represent the Q output of the Nth stage of the counter.
When A is “1”, 216 is selected for both states of B.
However, when B is “0”, normal counting is interrupted and
the 9th counter stage receives its clock directly from the
oscillator (i.e., effectively outputting 28).
The Q/Q select output control pin provides for a choice of
output level. When the counter is in a reset condition and
Q/Q select pin is set to a “0” the Q output is a “0”. Corre-
spondingly, when Q/Q select pin is set to a “1” the Q output
is a “1”.
When the mode control pin is set to a “1”, the selected
count is continually transmitted to the output. But, with
mode pin “0” and after a reset condition the RS flip-flop
resets (see Logic Diagram), counting commences and after
2n1 counts the RS flip-flop sets which causes the output to
change state. Hence, after another 2n1 counts the output
will not change. Thus, a Master Reset pulse must be
applied or a change in the mode pin level is required to
reset the single cycle operation.
Typical RC Oscillator
Characteristics
RC Oscillator Frequency as a
Function of RTC and C
Solid Line = RTC = 56 k, RS = 1 kand C = 1000 pF
f = 10.2 kHz @ VDD = 10V and TA = 25°
Dashed Line = RTC = 56 k, RS = 120 kand C = 1000 pF
f = 7.75 kHz @ VDD = 10V and TA = 25°
Line A: f as a function of C and (RTC = 56 k; RS = 120k
Line B: f as a function of RTC and (C = 100 pF; RS = 2 RTC
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CD4541BC Даташит, Описание, Даташиты
Oscillator Circuit Using RC Configuration
Logic Diagram
VDD = Pin 14
VSS = Pin 7
3 www.fairchildsemi.com










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