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PDF CD4723BC Data sheet ( Hoja de datos )
| Número de pieza | CD4723BC | |
| Descripción | Dual 4-Bit/ 8-Bit Addressable Latch | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de CD4723BC (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
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February 1988
CD4723BM CD4723BC Dual 4-Bit Addressable Latch
CD4724BM CD4724BC 8-Bit Addressable Latch
General Description
The CD4723B is a dual 4-bit addressable latch with com-
mon control inputs including two address inputs (A0 A1)
an active low enable input (E) and an active high clear input
(CL) Each latch has a data input (D) and four outputs (Q0 –
Q3) The CD4724B is an 8-bit addressable latch with three
address inputs (A0–A2) an active low enable input (E) ac-
tive high clear input (CL) a data input (D) and eight outputs
(Q0 – Q7)
Data is entered into a particular bit in the latch when that is
addressed by the address inputs and the enable (E) is low
Data entry is inhibited when enable (E) is high
When clear (CL) and enable (E) are high all outputs are low
When clear (CL) is high and enable (E) is low the channel
demultiplexing occurs The bit that is addressed has an ac-
tive output which follows the data input while all unad-
dressed bits are held low When operating in the address-
able latch mode (E e CL e low) changing more than one
bit of the address could impose a transient wrong address
Therefore this should only be done while in the memory
mode (E e high CL e low)
Features
Y Wide supply voltage range
3 0V to 15V
Y High noise immunity
Y Low power TTL
compatibility
0 45 VDD (typ )
fan out of 2 driving 74L
or 1 driving 74LS
Y Serial to parallel capability
Y Storage register capability
Y Random (addressable) data entry
Y Active high demultiplexing capability
Y Common active high clear
Connection Diagrams
CD4723B
Dual-In-Line Package
CD4724B
Dual-In-Line Package
Order Number CD4723B or
CD4724B
Top View
Truth Table
TL F 6003–1
Top View
TL F 6003 – 2
Mode Selection
E CL
Addressed
Latch
Unaddressed
Latch
L L Follows Data
Holds Previous Data
H
L
Hold Previous Data
Holds Previous Data
L H Follows Data
Reset to ‘‘0’’
H H Reset to ‘0’’
Reset to ‘‘0’’
Mode
Addressable Latch
Memory
Demultiplexer
Clear
C1995 National Semiconductor Corporation TL F 6003
RRD-B30M105 Printed in U S A
1 page  
Logic Diagrams
CD4723B
TL F 6003 – 3
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet CD4723BC.PDF ] | |
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| CD4723BC | Dual 4-Bit/ 8-Bit Addressable Latch | National Semiconductor |
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