CDP1878 Datasheet PDF - GE
| Part Number | CDP1878 | |
| Description | CMOS Dual Counter-Timer | |
| Manufacturers | GE | |
| Logo |  |
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CMOS Peripherals
CDP1878, CDP1878C
TNT
TAO
TAO
TAG
TACL
Rii
X-OIMEM
TPBiWR
TPA
CS
AO
AI
A2
VSS
3
4
7
8
9
10
II
12
13
14
TOP
28 VDD
27 DB7
26 DB6
25 DBS
24 DB4
23 DB3
22 OB2
21 OBI
20 DBO
19 TBO
18 TIll
17 TBG
16 TBCL
IS mET
VIEW
92CS-34626
TERMINAL ASSIGNMENT
CMOS Dual Counter-Timer
Features:
• Compatible with general-purpose and CDP1BOO-series
microprocessor systems
• Two 16-bit down-counters and two B-bit control registers
• 5 modes including a versatile variable-duty cycle mode
• Programmable gate-level select
• Two-complemented output pins for each counter-timer
• Software-controlled interrupt output
• Addressable in memory space or CDP1BOO-series I/O space
The RCA-CDP1878 and CDP1878C8 are dual counter-
timers consisting of two 16-bit programmable down
counters that are independently controlled by separate
control registers. The value in the registers determine the
mode of operation and control functions. Counters and
registers are directly addressable in memory space by any
general-industry-type microprocessors, in addition to
input/output mapping with the CDP1800-series micropro-
cessors.
Each counter-timer can be configured in five' modes with
the additional flexibility of gate-level control. The control
registers in addition to mode formatting, allow software
start and stop, interrupt enable, and an optional read
control that allows a stable readout from the counters. Each
counter-timer has software control of a common interrupt
output with an interrupt status register Indicating which
counter-timer has timed out.
In addition to the interrupt output, true and complemented
outputs are provided for each counter-timer for control of
peripheral devices.
The CDP1878 and CDP1878C are functionally identical.
They differ in that the CDP1878 has a recommended
operating voltage range of 4 to 10.5 volts, and the
CDP1878C has a recommended operating voltage range of
4 to 6.5 volts. These types are supplied in 28-lead dual-in-
line ceramic packages (0 suffix), and 28-lead dual-in-line
plastic packages (E suffix).
toFormerly RCA Dev. Type No. TA1098l and TA10981C, respectivel'
4
Table I - Mode Description
Mode
Function
1 Timeout
Outouts chance when clock decrements counter to "0"
2 Timeout Strobe
One clockwide output pulse when clock decrements
counJer to "0"
3 Gate-Controlled One Shot Outputs c,hange when clock decrements counter to "0".
Retriggerable
4 Rate Generator
Reoetitive clockwide outout oulse
5 Variable-Duty Cycle
Repetitive output with programmed duty cycle
Application
Event counter
Trigger pulse
Time-delay generation
Time-base....9.enerator
Motor control
OPERATING CONDITIONS at TA=Full Package-Temperature Range. For maximum reliability.
operating condition. should be selected 10 that operation II alwaYI within the following range.:
CHARACTERISTIC
DC Operating Voltage 8ange
Input Voltage Range
Maximum Clock Input Rise or
Fall Time
tr,tf
Minimum Clock Pulse Width
tWL, tWH
Maximum Clock Input Frequency,
fCl
LIMITS
CDP1878
Min. Max.
4 10.5
V!,:!,: VDD
CDP1878C
Min. Max,
4 6.5
Vss VjID
- 5- 5
200 200
DC 1 DC 1
UNITS
V
ps
ns
MHz
File Number 1341
_______________________________________________________________ 439
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_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Peripherals
CDP1878, CDP1878C
Functional Description-See Fig. 1
The dual counter-timer consists of two programmable 16-
bit down counters. separately addressable and controlled
by two independent 8-bit control registers. The word in the
control register determines the mode and type of operation
that the counter-timer performs. Writing to or reading from
a counter or register is enabled by selective addressing
during a write or read cycle. The data is placed on the data
bus by the microprocessor during the write cycle or read
from the counter during the read cycle. Data to and from
the counters and to the control registers is in binary format.
Each counter-timer consists of three parts. The first is the
counter itself, a 16-bit down counter that is decremented on
the trailing edge of the clock input. The second is the jam
register that receives the data when the counter is written
to. The word in the control register determines when the
jam register value is placed into the counter. The third part
is the holding register that places the counter value on the
data bus when the counter is read.
When the counter has decremented to zero, three events
occur. The first involves the common interrupt output pin
that, if enabled, becomes active low. The second is the
setting of a bit in the interrupt status register. This register
can be read to determine which counter-timer has timed
out. The third event is the logic change of the complemented
output pins.
In addition to the clock input used to decrement the
counter, a gate input is available to enable or initiate
operation. The counter-timers are independent and can
have different mode operations.
Write Operation
The counters and registers are separately addressable and
are programmed via the data bus when the chip is selected
with the TPB/WR pin active. Normal sequencing requires
that the counter jam register. be loaded first with the
required value (most significant and least significant byte
in any order), and then the control register be accessed and
loaded with the control word. The trailing edge of the
TPB/WR pulse will latch the control word into the control
register. The trailing edge of the first clock to occur with
gate valid will cause the counter to be jammed with Its initial
value. The counter will decrement on the trailing edge of
succeeding clocks as long as the gate is valid, until it
reaches zero. The output levels will then change, and if
enabled, the interrupt output will become active and the
appropriate timer bit will be set in the interrupt status
register. The interrupt output and the interrupt status
register can be cleared (to their inactive state) by addressing
the control register with the TPB/WR' line active. For
example, if counter A times out, control register A must be
accessed to reset the interrupt output high and reset the
timer A bit in the status register low. Timer B bit in the status
register will be unaffected.
Read Operation
Each counter has a holding register that is continuously
being updated by the counter and is accessed when the
counter is addressed during read cycles. Counter reads are
accomplished by halting the holding register and then
reading it, or by reading the holding register directly. If the
holding register is read directly, data will appear on the bus
if the counters are addressed with the RD line active.
However, if the clock decrements the counter between the
two read operations (most and least significant byte). an
inaccurate value will be read. To preclude this from
happening, writing a "1" into bit 60f the control register and
then addressing and reading the counter will result in a
stable reading. This operation prevents the holding register
from being updated by the counter and does not affect the
counter's operation.
The interrupt status register is read by addressing either
control register with the RD line active. A "1" in bit 7
indicates Timer A has timed out and a "1" in bit 6 indicates
Timer B has timed out. Bits 0-5 are zeros.
Control Register
~J
1Je=mEnEabnlee.dle
O=DI• •bled
Holding Reglater Control
1=Fre.ze Holding Register
0= Update Continuously
Start/Slop Control
1=918rt Counter - - - - - '
O"Stop Count.r
Lt '--..---'
Gate Level Select
1=Posltlve (High)
O=Neg.tlve (Low)
Interrupt Enable
1=Enabl.d
O=Olsabled
Mode Select
001=Mode 1
010-Mode 2
·011=Mode 3
100=Mode 4
101=Mode 5
·Plus Bit 7=0
III
Bltl 0, 1 and 2 - Mode Selects-See Mode Timing Diagrams (Figs. 2, 3, 4, 5 and 6).
Mode 1 -
Mode 2 -
Mode 3 -
Mode 4 -
Mode 5 -
Timeout
Timeout Strobe
Gate Controlled One Shot
Rate Generator
Variable-Duty Cycle
No Mode selected. Counter outputs unaffected.
Bit 7
-
-
Bit 2
0
0
BI11
0
1
BIIO
1
0
00 1 1
- 1 () 0
- 101
- 000
Note: When selectinll...!..!!!ode, the timer outputs TAO and
TBO are set low, and TAO and ftiO are set high. If bits 0,1
and 2 are all zero's when the control register is loaded, no
mode is selected, and the counter-timer outputs are
unaffected. Issuing mode 6 will cause an indeterminate
condition of the counter, issuing mode 7 is equivalent to
issuing mode 5.
___________________________________________ 443
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