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CDP65C51 PDF даташит

Спецификация CDP65C51 изготовлена ​​​​«GE» и имеет функцию, называемую «CMOS Asynchronous Communications Interface Adapter».

Детали детали

Номер произв CDP65C51
Описание CMOS Asynchronous Communications Interface Adapter
Производители GE
логотип GE логотип 

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CDP65C51 Даташит, Описание, Даташиты
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _CMOS Peripherals
Advance Information
TERMINAL ASSIGNMENT
vss
CSO
C51
RES
Rx C
XTLI
XTL
RTS
CTS
TxD
DTR
RxO
RSO
RS I
28
27
26
25
2.
23
7 22
8 21
20
10 I.
" 18
12 17
13 16
I. 15
TOP VIEW
R/W
~2
!l!1l
07
D6
D5
0"
03
02
01
DO
=
DCD
VDD
92CS-36774
CDP65C51
CMOS Asynchronous Communications
Interface Adapter (ACIA)
Features:
• Compatible with 8-blt microprocessors
• Full duplex operation with buffered
receiver and transmitter
• Data set/modem control functions
• Internal baud-rate generator with 15
programmable baud rates (50 to 19,200)
• Program-selectable internally or externally
controlled receiver rate
The RCA-CDP65C51 Asynchronous Communications Inter-
face Adapter (ACIA) provides an easily implemented,
program-controlled interface between 8-bit micropro-
cessor-based systems and serial communication data sets
and modems.
The CDP65C51 has an internal baud-rate generator. This
feature eliminates the need for multiple component support
circuits, a crystal being the only other part required. The
Transmitter baud rate can be selected under program
control to be either 1 of 15 different rates from 50 to 19,200
baud, or 1/16 times an external clock rate. The Receiver
baud rate may be selected under program control to be
either the Transmitter rate, or at 1/16 times an external
clock rate The CDP65C51 has programmable word lengths
of 5,6,7, or 8 bits; even, odd, or no panty; 1, 1V2, or 2 stop
bits
The CDP65C51 is designed for maximum programmed
control from the CPU, to simplify hardware implementation.
Three separate registers permit the CPU to easily select the
CDP65C51 operating modes and data-checking parameters
and determine operational status.
The Command Register controls parity, receiver echo
mode, transmitter interrupt control, the state of the RTS
line, receiver interrupt control, and the state of the DTR line.
The Control Register controls the number of stop bits, word
length, receiver clock source, and baud rate.
• Operates at baud rates up to 250,000 via
proper crystal or clock selection
• Programmable word lengths, number of stop
bits, and parity-bit generation and detection
• Programmable interrupt control
• Program reset
• Program-selectable serial echo mode
• Two chip selects
• 4-MHz, 2 MHz or 1 MHz operation (CDP65C51-4,
CDP65C51-2, CDP65C51-1, respectively)
• Single 3 V to 6 V power supply
• Full TTL compatibility
The Status Register indicates the states of the IRQ, DSR,
and DCD lines, Transmitter and Receiver Data Registers,
and Overrun, Framing, and Panty Error conditions.
The Transmitter and Receiver Data Registers are used for
temporary data storage by the CDP65C51 Transmit and
Receive circuits.
The CDP65C51-1, CDP65C51-2, and CDP65C51-4 are
capable of interfaCing with microprocessors with cycle
times of 1 MHz, 2 MHz and 4 MHz, respectively.
The CDP65C51 IS supplied in 28-lead, hermetic, dual-in-line
side brazed ceramic packages (D suffix), in 28-lead, dual-in-
line plastiC packages (E suffix) and in 28-lead dual-ln-Iine
small-outline (SO) packages (M) suffix.
File Number 1470
______________________________________________________________ 487









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CDP65C51 Даташит, Описание, Даташиты
CMOS Perlpherals_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CDP65C51
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (VOO)
(Voltage referenced to Vss terminal) .................................................................... -0.5 to +7 V
INPUT VOLTAGE RANGE, ALL INPUTS ........................................................... -0.5 to Voo +0.5 V
DC INPUT CURRENT, ANY ONE INPUT .................................................................... ±10 mA
POWER DISSIPATION PER PACKAGE (Po)'
ForTA=-40to+60°C{PACKAGETYPEE) .............................................................. 500mW
For TA = +60 to +85°C (PACKAGE TYPE E) ................................. Derate Linearly at 8 mW/oC to 300 mW
ForTA = -55 to +100°C (PACKAGE TYPE D) ............................................................. 500 mW
For TA = +100 to +125°C (PACKAGE TYPE D) ............................... Derate Linearly at 8 mW/oC to 300 mW
For TA = -40 to +85°C (PACKAGE TYPE M), ............................................................. 425 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
For TA = FULL PACKAGE..TEMPERATURE RANGE (All Package Types) .................................... 100 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE 0 ............................................................................... -55 to +125°C
PACKAGE TYPE E and M .......................................................................... -40 to +85°C
STORAGE-TEMPERATURE RANGE (Tstg) ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• -65 to +150°C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 In. (1.59 ± 0.79 mm) from case for 10 s maximum .................................... +265°C
• Printed-circuit board mount: 57 mm x 57 mm minimum area x 1.6 mm thick Gl0 epoxy glass, or equivalent.
RECOMMENDED OPERATING CONDITIONS at TA = _40° to +85° C
For maximum reliability, nominal operating conditioils should be selected so that operation is always
within the following ranges:
CHARACTERISTIC
DC Operating Voltage Range
Input Voltage Range
LIMITS
IMin.
Max.
3 I6
Vss I Voo
UNITS
V
STATIC ELECTRICAL CHARACTERISTICS at TA = _40° to +85°C, Voo = 5V ± 5%
CHARACTERISTIC
Quiescent Device Current
Output Low Current (Sinking): VOL = 0.4 V
(00-07, TxD, RxC,RTS, DTR, IRQ
Output High Current (Sourcing): VOH = 4.6 V
(00-07, TxD, RxC, RTS, DTR)
Output Low Voltage: ILOAO = 1.6 mA
(00-07, TxO, RxC, RTS, DTR, IRQ)
Output High Voltage: ILoAO - -1.6 mA
(00-D7,TxO, RxC, RTS, DTR)
Input Low Voltage
Input High Voltage
(Except XTLI and XTLO)
(XTLI and XTLO)
Input Leakage Current: V'N = 0 to 5 V
(</J2, Riw, RES, CSO, CSt, RSO, RS1, CTS, RxO, DCD, DSR)
Input Leakage Current for High Impedance State (00-07)
Output Leakage Current (off state): VOUT = 5 V (IRQ)
I nput Capacitance (except XTLI and XTLO)
~. Capacitance
100
10L
10H
VOL
VOH
V'L
V'H
I'N
Irs,
10FF
C'N
COUT
Min.
-
1.6
-1.6
-
4.6
Vss
2
3
-
-
-
-
-
LIMITS
Typ.
50
-
-
-
-
-
-
-
-
-
-
-
-
Max.
200
-
-
0.4
-
0.8
Voo
Voo
±1
±1.2
2
10
10
UNITS
/lA
mA
mA
V
V
V
V
/lA
/lA
/lA
pF
pF
488 _________________________________________________________________









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CDP65C51 Даташит, Описание, Даташиты
_____________________________CMOS perlpnerals
CDP65C51 INTERFACE REQUIREMENTS
CDP65C51
This section describes the interface requirements for the
CDP65C51 ACIA. Fig. 1 is the Interface Diagram and the
Terminal Diagram shows the pin-out configuration for the
CDP65C51.
00-07
eTs
TxD
DeD
DSR
Rxe
XTLI
XTLO
00-07 (Data Bus) (18-25)
The DO-D7 pins are the eight data lines used to transfer data
between the processor and the CDP65C51. These lines are
bi-directional and are normally high-impedance except
during Read cycles when the CDP65C51 is selected.
CSO, CSl (Chip Selects) (2, 3)
The two chip-select inputs are normally connected to the
processor address lines either directly or through decoders.
The CDP65C51 is selected when CSO is high and CS1 is
low.
RSO, RSl (Register Selects) (13, 14)
The two register-select lines are normally connected to the
processor address lines to allow the processor to select the
various CDP65C51 internal registers. The following table
shows the internal register-select coding.
TABLE I
RSl RSO
Write
Read
0
0
Transmit Data
Receiver Data
Register
Register
0 1 Programmed Reset Status Register
(Data is "Don't
Care")
10
Command Register
11
Control Register
92CM-36860
Fig. 1 - CDP65C51 interface diagram.
MICROPROCESSOR INTERFACE
SIGNAL DESCRIPTION
RES (Reset) (4)
During system initialization a low on the RES input will
cause a hardware reset to occur. The Command Register
and the Control Register will be cleared. The Status
Registerwill be cleared with the exception of the indications
of Data Set Ready and Data Carrier Detect, which are
externally controlled by the DSR and I5CD lines, and the
transmitter Empty bit, which will be set. A hardware reset is
required after power-up.
</>2 (Input Clock) (27)
The Input clock is the system </>2 clock and is used to clock
all data transfers between the system microprocessor and
the CDP65C51.
R/W (Read/Write) (28)
The R/W input, generated by the microprocessor, is used to
control the direction of data transfers. A high on the R/W pin
allows the processor to read the data supplied by the
CDP65C51, a low allows a write to the CDP65C51.
IRQ (Interrupt Request) (26)
The IRQ pi n IS an interru pt output from the interru pt control
logic. It is an open drain output, permitting several devices
to be connected to the commonTI'fQ microprocessor input.
Normally at high level, IRQ goes low when an interrupt
occurs.
Only the Command and Control registers are read/write.
The Programmed Reset operation does not cause any data
transfer, but is used to clear bits 4 through 0 in the
Command Register and bit 2 in the Status Register. The
Control Register is unchanged by a Programmed Reset. It
should be noted that the Programmed Reset is slightly
different from the Hardware Reset (RES); these differences
are shown in Figs. 3, 4 and 5.
ACIA/MODEM INTERFACE
SIGNAL DESCRIPTION
XTLI, XTLO (Crystal Pins) (6, 7)
These pins are normally directly connected to the external
crystal (1.8432 MHz) used to derive the various baud rates
(see "Generation of Non-Standard Baud Rates"). Alterna-
tively, an externally generated clock may be used to drive
the XTLI pin, in which case the XTLO pin must float. XTLI is
the input pin for the transmit clock.
TxD (Transmit Data) (10)
The TxD output line is used to transfer serial NRZ
(nonreturn-to-zero) data to the modem. The LSB (least
significant bit) of the Transmit Data Register is the first data
bit transmitted and the rate of data transmission is
determined by the baud rate selected or under control of an
external clock. This selection is made by programming the
Control Register.
RxD (Receive Data) (12)
The RxD input line is used to transfer serial NRZ data into
the ACIA from the modem, LSB first. The receiver data rate
is either the programmed baud rate or under the control of
an externally generated receiver clock. The selection is
made by programming the Control Register.
------___________________________________________________________ 489










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