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CDP6823 PDF даташит

Спецификация CDP6823 изготовлена ​​​​«GE» и имеет функцию, называемую «CMOS Parallel Interface».

Детали детали

Номер произв CDP6823
Описание CMOS Parallel Interface
Производители GE
логотип GE логотип 

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CDP6823 Даташит, Описание, Даташиты
CMOS Peripherals
CDP6823
TERMINAL ASSIGNMENT
PCI Voo
PCI PC3
PCO
PAD
PC4/CA1
PC~/CA2
PAl PC6/CB
Poll PCrlce2
PAS
P80
Pol'" P8'
PAil P82
PAl PIJ
PAl' P8"
ADO
P85
AO' PBe
mA02
AD3
PS1
AD4 mrT'
An os
ADe R/ii'
V"A01
---.=-_-',"',-
AS
Jr
TOP VIEW
4G-Lead Plcklll"
Advance Information
CMOS Parallel Interface
Featurel:
• Four port C I/O pins may be used as
Control Lines for:
• 24 Individual programmed I/O pins
Four interruput inputs
• MOTEL circuit for bus compatibility
Input byte latch
with many microprocessors
Output pulse
• Multiplexed bus compatible with:
Handshake activity
CDP6805E2 and competitive
• 15 registers addressed as memory
microprocessors
locations
• Data direction registers for ports A, S, • Handshake control logic for Input and
andC
output peripheral operation
• Reset Input to clear interrupts and
• Interrupt output pin
Initialize Internal registers
• 3 volt to 5.5 volt operating Voo
The RCA-C0P6823 CMOS parallel interface (CPI) provides
a universal means of interfacing external signals with the
C0P6805E2 CMOS microprocessor and other multiplexed
bus microprocessors. The unique MOTEL circuit on-chip
allows direct Interfacing to most industry CMOS
microprocessors, as well as many NMOS MPUs.
The C0P6B23 CPI includes three bidirectlonal8-bit ports or
24 1/0 pins. Each 1/0 line may be separately established as
an Input or an output under program control via data
direction registers associated with each port. Using the bit
change and test Instructions of the C0P6805E2, each
individual I/O pin can be separately accessed. All port
registers are readlwrlte bytes to accommodate read-
modify-write Instructions.
The C0P6B23Is supplied In a 40-lead hermetic dual-in-line
side-brazed ceramic package (0 suffix), In a 4o-Iead dual-
In-line plastiC package (E suffix) and In a 44-lead plastiC
chlp-carrler package (Q suffix).
The RCA-COP6823 is equivalent to and is a direct
replacement for the Industry type MC146823.
'"
'A"""
AD5
ASEDS
RI\IV Control
R"E"S'rT
Inputs
"
TERMINAL ASSIGNMENT
PA' Ne
PA! PC7lCB2
PA'
PA. 'D
PBD
PB.
PAl 11
12----=f--- - ..PA7
IADD n
TOplYIEW
~!5 PB.
PB'
33 PB.
AD' ~
ADZ 15
I
~ PB'
31 PBe
AD! 16
30 pa?
Ne 17
29 fRO
18 19 20 21 22 23 24 25 26 27 28
= It;> I~ :
I~ ~ Ii!
:!IE ..
92CS -40940
44-L.ad Pla.tlc Chip-Carrier Packlll'
Fig. 1 - Functional block diagram.
'"Pc>
PC3
PC4ICAI
PC5/CA2
pee/CBI
PC71CB2
File Number 1377
598 ______________________________________________________________









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CDP6823 Даташит, Описание, Даташиты
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Peripherals
MAXIMUM RATINGS (Vo(tages reference to VSS)
Ratings
Symbol
Value
Supply Voltage
All Input Voltages
Current Drain per Pin Excluding
VDD and VSS
VDD
-03to+8
Vin VSS-O 5 to VDD+O 5
I 10
Operating Temperature Range
Storage Temperature Range
TA
Tstg
-40 to +85
-55 to +150
Unit
V
V
rnA
·C
·C
THERMAL CHARACTERISTICS
Characteristics
hermal Hes stance
Ceramic Dual-In-Line
Plastic Dual-ln-L1ne
Plastic Chip-Carrier
Symbol Value
8JA
50
100
70
Unit
·C/W
CDP6823
This device contains circuitry to protect the
inputs against damage due to high static
voltages or electric fields; however. it is
advised that normal precautions betaken to
avoid application of any voltage higher than
maximum rated voltages to this high-im-
pedance circuit. For proper operation it is
recommended' that V,n and Vou• be con-
strained to the range Vss ;::: (V,n or Vou.) ;:::
Voo. Leakage currents are reduced and
reliability of operation is enhanced if unused
inputs are tied to an appropriate logic
voltage level (e.g.• either Vss or Voo).
DC ELECTRICAL CHARACTERISTICS (VDD=5 Vdc ± 10%, Vss=O Vdc TA=O·C to 70·C unless otherwise noted)
Parameter
Symbol
Min
Max
Output Voltage IILoads 10 p.A)
Output High Voltage
II Load = - 1 6 rnA) ADO-AD7
IILoad= -02 rnA) PAO-PA7, PCO-PC7
IILoad= -036 rnA) PBO-PB7
VOL
VOH
VOH
VOH
VOH
-
VDD-O 1
41
41
41
01
-
VDD
VDD
VDD
Output Low Voltage
II Load = 16 rnA) ADO-AD7, PBO-PB7
(ILoad=O 8 mAl PAO-PA7, PCO-PC7
II Load = 1 rnA) IRQ
cr,Input High Voltage, ADO-AD7, AS, DS, R/W, PAO-PA7, PBO-PB7, PCO-PC7
RESET
Input Low Voltage (All Inputs)
QUiescent Current - No dc Loads
(All Ports Programmed as Inputs, All Inputs= VDD - 02 V)
VOL
VOL
VOL
VIH
VIH
VIL
VSS
VSS
VSS
VDD-20
VDD-O 8
VSS
04
04
04
VDD
VDD
08
IDD -
160
Total Supply Current
(All Ports Programmed as Inputs, CE= VIL, tcyc= 1 p.s)
Input Current, cr, AS, R/W, DS, FftSET
H,-Z State Leakage, ADO-AD7, PAO-PA7, P80-P87, peO-PC7
IDD -
3
lin - ±1
ITSL
±10
Unit
V
V
V
V
V
V
p.A
rnA
p.A
p.A
III
TTL EqUivalent
VDD
Test
POint
o - -......I - - -......I-----i. .-
.......
C
CMOS EqUivalent
TestPolnt~
For all outputs except IRCi
C=50 pF, All Ports
= 130 pF, ADO-AD7
I1
C
for VDD=5 V ± 10%
_
Pin
ADO-AD7
PAO-PA7, PCO-PC7
PBO-PB7
Rl
255k
20k
115k
R2
2k
432k
21k
C
130 pF
50 pF
50 pF
402k
90pF
Fig. 2 - Equivalent test loads.
- - - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 599









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CDP6823 Даташит, Описание, Даташиты
CMOS Peripherals
CDP6823
BUS TIMING IVDD=5 Vdc ± 10% VSS=O Vdc TA=O· to 70·C unless otherwise noted)
Ident.
Number
Characteristics
Symbol Min
Max
Unit
1 Cycle Time
tcyc 1000
dc
ns
2 Pulse Width, DS/E Low or FIO/WR High
PWEL
300
ns
3 Pulse Width, DS/E High or RU/WR Low
PWEH
325
ns
4 Input Rise and Fall Time
tr,tf 30 ns
8 R/W Hold Time
cr13 R/'ll and Setup Time Before DS/E
15 Chip Enable Hold Time
tRWH
10
tRWS
25
tCH 0 -
ns
ns
ns
18 Read Data Hold Time
21 Write Data Hold Time
tDHR
tDHW
10 100
0
ns
ns
24 Muxed Address Valid Time to ASI ALE Fall
25 Muxed Address Hold Time
26 Delay Time DS/E to ASI ALE Rise
tASL
25
tAHL
20
tASD 60 -
ns
ns
ns
27 Pulse Width, ASI ALE High
28 Delay Time, ASI ALE to DS/E Rise
30 Peripheral Output Data Delay Time from DS/E or AD
PWASH
tASED
tDDR
170
60
20
-
240
ns
ns
ns
31 Peripheral Data Setup Time
tDSW
220
-
ns
NOTE Designations E, ALE, RD, and WR refer to signals from alternative microprocessor signals
AS
DS
R/W
ADO-
AD7
WRITE
~----~311}-------~
~~~~~----------~zr1~
Write Data Valid
~'-----(:30)------I
ADO-
AD7
READ
NOTE VHIGH=VDD-2 V, VLOW=O 8 V. for VDO=5 V ± 10%
Read Data
Valid
Fig. 3 - Bus timing diagram.
600 _______________________________________________________________










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Номер в каталогеОписаниеПроизводители
CDP6823CMOS Parallel InterfaceGE
GE
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Harris Semiconductor

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