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PDF CDP1826C Data sheet ( Hoja de datos )
| Número de pieza | CDP1826C | |
| Descripción | CMOS 64-Word x 8-Bit Static Random-Access Memory | |
| Fabricantes | GE | |
| Logotipo |  |
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_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Random-Access Memories (RAMs)
BUSO
BUS I
BUS 2
BUS 3
BUS 4
BUS 5
BUS 6
BUS 7
CSI
-en
V5S
I 22 Voo
2 21 AO
3 20 CS/A5
4 19 AI
5 18 A2
6 17 A3
7 16 A4
8 15 TPA
9 14 MRO
10 13 flWl!
II 12 CEO
TOP VIEW
92CS-34034
TERMINAL ASSIGNMENT
CMOS 64-Word X a-Bit Static
Random-Access Memory
Features:
• Ideal for small, low-power RAM Memory requirements
In microprocessor and microcomputer applications
• Interfaces with CDP1BOO-series microprocessors
without additional address decoding
• DaiSY chain feature to further reduce external
decoding needs
• Multiple chip-select Inputs for versatility
• Single voltage supply
• No clock or precharge reqUIred
CDP1826C
The RCA CDP1B26C IS a general-purpose, fully static, 64-
word x 8-blt random-access memory, for use In CDP1800
series or other microprocessor systems where minimum
component count and/or price performance and simplicity
in use are deSirable.
The CDP1B26C has 8 common data Input and data-output
terminals with 3-state capability for direct connection to a
standard bi-directional data bus Two chip-select Inputs-
CSl and CS2 - are provided to simplify memory-system
expansion. An additional select Pin, CS/A5, IS prOVided to
enable the CDP1826C to be selected directly from the
CDP1800 multiplexed address bus without additional latch-
Ing or decoding In an 1800 system, the CS/A5 pin can be
tied to any MA address line from the CDP1800 processor. A
TPA Input IS prOVided to latch the high-order bit of thiS
address line as a chip-select for the CDP1826C. If this
CS/A5 Input is latched high, and IfCS= 1 and CS2 =Oatthe
appropriate time In the memory cycle, the CDP1826C will
be enabled for writing or reading. In a non-1800 system, the
TPA pin can be tied high, and the CS/A5 pin can be used as
a normal address Input
The six Input-address buffers are gated with the Chip-select
function to reduce standby current when thedevlce is dese-
lected, as well as to provide for a Simplified power down
mode by reducing address buffer sensitivity to long fall
times from address drivers which are being powered down
l¢q
ADOR BUS
TPA
----
-----
AOoR BUS
TPA
NO-N2 MAo
TPB
Q
DATA )
ROM
RAM
CoPI826C
iiRD
CEO
MRO
MWR
CPU
CoPI800
SERIES
SCO SCI
INTERRUPT
oMA-IN OMA:miT
EFI-EF4
I/O CONTROL)
" "/1 a-BIT BIDIRECTIONAL DATA BUS
1/
92CM-34043
Fig 1 - TYPical CDP1802 mlcrocprocessor system
File Number 1311
_____________________________________________ 671
1 page  
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Random-Access Memories (RAMs)
CDP1826C
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = - 40 to + 85° C, Voo = 5 V ± 5%,
Input t"t, = 10 ns' CL = 50 pF and 1 TTL Load
LIMITS
CHARACTERISTIC
MIN·t
CDP1826C
I TYP.-
I
Read - Cycle Times (Figs 4 and 5)
Address to TPA Setup
100 -
Address to TPA Hold
Access from
Address Change
TPA Pulse Width
tASH
100
tAH
-
TAA
200
-
500
-
Output Valid from
MRD
Access from
Chip Select
CEO Delay from
TPA""lt..Edge
IimlS to CEO Delay
Oulput High ~ from
Invalid MRD
Oulput High ~ from
Chip Deselect
tpAW
tAM
tAc
tCA
IMC
IR....
ts ....
-
-
-
75
-
-
500
500
150
-
-
-
tTime required by a IIm,t dev,ce to allow for the indicated function
oTypical values are for T. = 25° C and nominal Voo.
MAX.
-
-
1000
-
1000
1000
300
-
125
225
UNITS
ns
AO-AS
TPA
LOW ORDER ADDRESS BYTE
CSI·CS2
'AC----"
VALID CHIP SELECT
'RHZ
CEO
BUS-------------+~HI~G~H~,7.M~PE~O~A7.N~C~E--------K
'AM ______---<~
VALID DATA
92CM-37721
Fig. 4 - Tlmmg waveforms for Read-cycle 1.
____________________________________________________________ 675
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet CDP1826C.PDF ] | |
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