CDP68HC68R2 Datasheet PDF - GE
| Part Number | CDP68HC68R2 | |
| Description | CMOS 128-Word and 256-Word by 8-Bit Static RAMs | |
| Manufacturers | GE | |
| Logo |  |
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_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Random-Access Memories (RAMs)
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M~~~O:I :O:SI
NC 3
VSS 4
VIEWTOP
6 CE
5 ss
92CS-3786!5
TERMINAL ASSIGNMENT
CDP68HC68R1, CDP68HC68R2
CMOS 128-Word (CDP68HC68R1) and
256-Word (CDP68HC68R2) by
8-Bit Static RAMs
Features:
• Fully static operation
• Operating voltage range:
3 VtoS.S V
• Typical standby current=1 pA
• Directly compatible with
RCA/Motorola SPI bus
• Separate data input and three-
state data output pins
• Input data and clock buffers
gated off with chip enable
• Automatic sequencing for fast
multiple-byte accesses
• Low minimum data retention
voltage: 2 V
• Wide operating temperature
range: -40· C to +8S· C
The RCA CDP68HC68R1 and CDP68HC68R2are 128-word
and 256-word by 8-bit static random-access memories,
respectively. The memories are intended for use in systems
utilizing a synchronous serial three-wire (clock, data in, and
data out) interface where minimum package size,
interconnect wiring, low power, and simplicity of use are
desirable. These parts will interface directly with RCA's
CDP68HC05D2, CDP68HC05C4, and CDP68HC05C8
microcomputers (providing the CPHA bit in the
microcomputer's SPI Control Register is set equal to 1). The
CDP68HC68R1 and CDP68HC68R2 are also compatible
with general-purpose microcomputers, including RCA's
CDP1804A and CDP6805 family, by utilizing I/O bits forthe
SPI (Serial Peripheral Interface) bus. Other industry
microcomputers such as the 80C51 can also interface to
these serial RAM's.
The CDP68HC68R1 and CDP68HC68R2 are supplied in
8-lead plastic Mini-DIP packages (E suffix).
TRUTH TABLE
MODE
DISABLED
& RESET
READ
OR
WRITE
SHIFT
CE
L
X
H
H
SIGNAL
B
SCK
MOSI
MISO
X
INPUT
INPUT
H
DISABLED
DISABLED
HIGHZ
CPOL=O,
' -L
-.rCPOL=1,
DATA BIT
LATCH
HIGHZ
DURING WRITE,
CURRENT DATA BIT
DURING READ
fCPOL=O,
L
' - -CPOL=1,
X NEXT DATA
BIT
NOTE:
MISO remains at a High Z until8 bits of data are ready to be shifted out during a Read and it remains at a HIGH Z during the
entire Write cycle.
The CPHA bit must be set = 1 in the Serial Perpherial Control Register of 6805 microcomputers in order to Communicate
with these devices.
File Number 1544
_______________________________________________________________ 679
|
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_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Random-Access Memories (RAMs)
CDP68HC68R1, CDP68HC68R2
RAM address to automatically increment. Incrementing
continues after each transfer until the device is disabied.
After incrementing to 7FH on the CDP68HC68R1 or to FFH
on the CDP68HC68R2, the address will recycle to OOH and
CE'SS~
continue. Note that incrementing past 7FH on the CDP-
68HC68R2 causes the address to go to location 80H (i.e.,
location OOH of page 1). The programmer must take care to
keep track when crossing page boundaries.
{
SCK IIIIII11 III II III 111111111: I1II 1111I
~ ~,. . . -A-D -R-E-S -e-VT-E-r- DA-T-A-BY-T-E- ,. . . -DA-T-A-e-Y-T-E-:!: 1;-I-D-AT-A-BY-T-E--r~~~-rT
WRITE {MOSl: ...
~?:-----~
MOSl: 7""7"7~~ADDR-ESS-BVTE--P-;;~~~'"77"777/'"77"7i: ~
{
I.I~READ
Ml:SO-----------~
Wiff ADDRE SS {
ADDRESS
ADDRESS
ADDRESS
Fig. 5 - Multiple-byte transfers.
OYNAMIC ELECTRICAL CHARACTERISTICS - BUS TIMING VOO ±100f0,
VSS = 0 V dc, T A = -400 to +850 C, CL = 200 pF. See Figs. 6, 7 and 8.
92CM- 37718
IOENT.
NUMBER
CHARACTERISTIC
LIMITS (ALL TYPES)
IVOO=3.3 V VOO-5 V UNITS
Min. Max. Min. Max.
Q) Chip Enable Set-Up Time
0 Chip Enable after Clock Hold Time
@ Clock Width High
tevcv
tCVEX
tWH
200 -
250 -
400 -
100 -
125 -
200 -
0 Clock Width Low
® Data In to Clock Set-Up Time
0 Data In after Clock Hold Time
0 Clock to Data Propagation Delay
0 Chip Disable to Output High Z
@ Output Rise Time
@ Output Fall Time
tWL
tovey
tCYDX
tcvDV
tExDZ
t,
t.
400 - 200 -
200 - 100 -
200 - 100 -
-- 200
100
- 200 - 100
- 200 - 100
ns
- 200 - 100
0 Clock to Data Out Active
tcvax
- 200 - 100
® Clock Recovery Time
-tREC 200 - 200
____________________________________________ 683
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| Information | Total 7 Pages | |
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Featured Datasheets
| Part Number | Description | MFRS |
| CDP68HC68R1 | The function is CMOS 128-Word and 256-Word by 8-Bit Static RAMs. GE | |
| CDP68HC68R2 | The function is CMOS 128-Word and 256-Word by 8-Bit Static RAMs. GE | |
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