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PDF N121I6-L01 Data sheet ( Hoja de datos )
| Número de pieza | N121I6-L01 | |
| Descripción | TFT LCD Module | |
| Fabricantes | Chi Mei | |
| Logotipo |  |
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Doc No.: 1406X169
Issued Date:Apr. 04, 2007
Model No.: N121I6 -L01
Preliminary
TFT LCD Preliminary Specification
MODEL NO.: N121I6 - L01
Customer :
Approved by :
Note :
2007-04-25
15:29:53 CST
2007-04-10
15:48:38 CST
Approve by Dept.
Mgr.(QA RA)
yuan_chan(
/52760/54760)
Approve by Director hj_mao(
/13070)
Department
Manager(QA RA)
Director
Accept
Accept
1 / 30
Version 1.1
1 page  
Doc No.: 1406X169
Issued Date:Apr. 04, 2007
Model No.: N121I6 -L01
Preliminary
2 ABSOLUTE MAXIMUM RATINGS
2.1 ABSOLUTE RATINGS OF ENVIRONMENT
Item
Storage Temperature
Operating Ambient Temperature
Shock (Non-Operating)
Vibration (Non-Operating)
Note (1) (a) 90 %RH Max. (Ta
Symbol
TST
TOP
SNOP
VNOP
40 ºC).
Value
Min. Max.
-20 +60
0 +50
- 200/2
- 1.5
Unit
ºC
ºC
G/ms
G
Note
(1)
(1), (2)
(3), (5)
(4), (5)
(b) Wet-bulb temperature should be 39 ºC Max. (Ta > 40 ºC).
(c) No condensation.
Note (2) The temperature of panel display surface area should be 0 ºC Min. and 60 ºC Max.
Relative Humidity (%RH)
100
90
80
60
Operating Range
40
20
10 Storage Range
-40 -20
0 20 40 60 80
Temperature (ºC)
Note (3) 1 time for ± X, ± Y, ± Z. for Condition (200G / 2ms) is half Sine Wave,.
Note (4) 10 ~ 500 Hz, 30 min/cycle,1cycles for each X, Y, Z axis.
Note (5) At testing Vibration and Shock, the fixture in holding the module has to be hard and rigid
enough so that the module would not be twisted or bent by the fixture.
The fixing condition is shown as below:
At Room Temperature
LCD Module
Side Mount Fixing Screw
Gap=2mm
Bracket
Side Mount Fixing Screw
Stage
5 / 30
Version 1.1
5 Page 
5 INPUT TERMINAL PIN ASSIGNMENT
5.1 TFT LCD MODULE
Pin Symbol
Description
1 VSS Ground
2 VDD Power Supply +3.3 V
3 VDD Power Supply +3.3 V
4
VEDID
DDC +3.3 V
5 TEST Panel Self Test
6 CLKEDID DDC Clock
7 DataEDID DDC Data
8 Rxin0- LVDS Differential Data Input
9 Rxin0+ LVDS Differential Data Input
10 VSS Ground
11 Rxin1- LVDS Differential Data Input
12 Rxin1+ LVDS Differential Data Input
13 VSS Ground
14 Rxin2- LVDS Differential Data Input
15 Rxin2+ LVDS Differential Data Input
16 VSS Ground
17 CLK- LVDS Clock Data Input
18 CLK+ LVDS Clock Data Input
19 VSS Ground
20 VSS Ground
Note (1) Connector Part No.: DF19KR-20P-1H or equivalent
Note (2) User’s connector Part No: DF19G-20S-1C or equivalent
Polarity
Negative
Positive
Negative
Positive
Negative
Positive
Negative
Positive
-
-
Doc No.: 1406X169
Issued Date:Apr. 04, 2007
Model No.: N121I6 -L01
Preliminary
Remark
-
-
-
R0~R5,G0-
G1~G5,B0,B1
-
B2~B5,Hsync,Vsync,DE
LVDS Level
-
-
5.2 TIMING DIAGRAM OF LVDS INPUT SIGNAL
CLK+
Rxin2
Rxin1
Rxin0
T/7
IN20
DE
IN13
B1
IN6
G0
IN19
Vsync
IN12
B0
IN5
R5
IN18
IN17
IN16
Hsync
B5
B4
IN11
IN10
IN9
G5 G4 G3
IN4 IN3
IN2
R4 R3 R2
Signal for 1 DCLK Cycle (T)
IN15
B3
IN8
G2
IN1
R1
IN14
B2
IN7
G1
IN0
R0
11 / 30
Version 1.1
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet N121I6-L01.PDF ] | |
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