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CA3338A PDF даташит

Спецификация CA3338A изготовлена ​​​​«Intersil Corporation» и имеет функцию, называемую «CMOS Video Speed/ 8-Bit/ 50 MSPS/ R2R D/A Converters».

Детали детали

Номер произв CA3338A
Описание CMOS Video Speed/ 8-Bit/ 50 MSPS/ R2R D/A Converters
Производители Intersil Corporation
логотип Intersil Corporation логотип 

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CA3338A Даташит, Описание, Даташиты
CA3338, CA3338A
August 1997
CMOS Video Speed, 8-Bit,
50 MSPS, R2R D/A Converters
Features
• CMOS/SOS Low Power
• R2R Output, Segmented for Low “Glitch”
• CMOS/TTL Compatible Inputs
• Fast Settling: (Typ) to 1/2 LSB . . . . . . . . . . . . . . . . 20ns
• Feedthrough Latch for Clocked or Unclocked Use
• Accuracy (Typ) . . . . . . . . . . . . . . . . . . . . . . . . . ±0.5 LSB
• Data Complement Control
• High Update Rate (Typ) . . . . . . . . . . . . . . . . . . . . 50MHz
• Unipolar or Bipolar Operation
Applications
• TV/Video Display
• High Speed Oscilloscope Display
• Digital Waveform Generator
• Direct Digital Synthesis
Description
The CA3338 family are CMOS/SOS high speed R2R voltage
output digital-to-analog converters. They can operate from a
single +5V supply, at video speeds, and can produce
“rail-to-rail” output swings. Internal level shifters and a pin for
an optional second supply provide for an output range below
digital ground. The data complement control allows the inver-
sion of input data while the latch enable control provides
either feedthrough or latched operation. Both ends of the
R2R ladder network are available externally and may be
modulated for gain or offset adjustments. In addition, “glitch”
energy has been kept very low by segmenting and thermom-
eter encoding of the upper 3 bits.
The CA3338 is manufactured on a sapphire substrate to give
low dynamic power dissipation, low output capacitance, and
inherent latch-up resistance.
Pinout
CA3338, CA3338A
(PDIP, SBDIP, SOIC)
TOP VIEW
D7 1
D6 2
D5 3
D4 4
D3 5
D2 6
D1 7
VSS 8
16 VDD
15 LE
14 COMP
13 VREF+
12 VOUT
11 VREF-
10 VEE
9 D0
Ordering Information
PART LINEARITY TEMP.
NUMBER (INL, DNL) RANGE (oC) PACKAGE
PKG.
NO.
CA3338E ±1.0 LSB -40 to 85 16 Ld PDIP E16.3
CA3338AE ±0.75 LSB -40 to 85 16 Ld PDIP E16.3
CA3338D ±1.0 LSB -55 to 125 16 Ld SBDIP D16.3
CA3338AD ±0.75 LSB -55 to 125 16 Ld SBDIP D16.3
CA3338M ±1.0 LSB -40 to 85 16 Ld SOIC M16.3
CA3338AM ±0.75 LSB -40 to 85 16 Ld SOIC M16.3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
10-11
File Number 1850.2









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CA3338A Даташит, Описание, Даташиты
Functional Diagram
16
VDD
15
LE
CA3338, CA3338A
14
COMP
1
D7
2
D6
3
D5
4
D4
5
D3
6
D2
7
D1
9
D0
8
VSS
3-BIT
TO 7-LINE
THERMOMETER
ENCODER
LEVEL
SHIFTERS
FEEDTHROUGH
LATCHES
13
VREF+
8R
8R
12
8R VOUT
8R
R
4R
4R
R
2R
R
2R
R
2R
R
2R
R
2R
R
2R
2R
11
VREF-
10
R 160
VEE
10-12









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CA3338A Даташит, Описание, Даташиты
CA3338, CA3338A
Absolute Maximum Ratings
Thermal Information
DC Supply-Voltage Range . . . . . . . . . . . . . . . . . . . . . . -0.5V to +8V
(VDD - VSS or VDD - VEE, Whichever is Greater)
Input Voltage Range
Digital Inputs (LE, COMP D0 - D7) . . . . VSS - 0.5V to VDD + 0.5V
Analog Pins (VREF+, VREF-, VOUT) . . . . VDD - 8V to VDD + 0.5V
DC Input Current
Digital Inputs (LE, COMP, D0 - D7). . . . . . . . . . . . . . . . . . ±20mA
Recommended Supply Voltage Range. . . . . . . . . . . . . .4.5V to 7.5V
Operating Conditions
Temperature Range (TA)
Ceramic Package, D suffix
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
-55oC
to
125oC
Plastic Package, E suffix, M suffix . . . . . . . . . . . . . . -40oC to 85oC
Thermal Resistance (Typical, Note 1)
θJA (oC/W) θJC (oC/W)
SBDIP Package . . . . . . . . . . . . . . . . . .
75
24
PDIP Package . . . . . . . . . . . . . . . . . . . 100
N/A
SOIC Package . . . . . . . . . . . . . . . . . . . 100
N/A
Maximum Junction Temperature
Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC
Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range, TSTG . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications TA = 25oC, VDD = 5V, VREF+ = 4.608V, VSS = VEE = VREF- = GND, LE Clocked at 20MHz, RL 1 M,
Unless Otherwise Specified
PARAMETER
TEST CONDITIONS
ACCURACY
Resolution
Integral Linearity Error
CA3338
See Figure 4
CA3338A
Differential Linearity Error
CA3338
See Figure 4
CA3338A
Gain Error
CA3338
Input Code = FFHEX, See Figure 3
CA3338A
Offset Error
Input Code = 00HEX; See Figure 3
DIGITAL INPUT TIMING
Update Rate
To Maintain 1/2 LSB Settling
Update Rate
VREF- = VEE = -2.5V, VREF+ = +2.5V
Set Up Time tSU1
For Low Glitch
Set Up Time tSU2
For Data Store
Hold Time tH
For Data Store
Latch Pulse Width tW
For Data Store
Latch Pulse Width tW
VREF- = VEE = -2.5V, VREF+ = +2.5V
OUTPUT PARAMETERS RL Adjusted for 1VP-P Output
Output Delay tD1
From LE Edge
Output Delay tD2
From Data Changing
Rise Time tr
Settling Time tS
10% to 90% of Output
10% to Settling to 1/2 LSB
Output Impedance
VREF+ = 6V, VDD = 6V
Glitch Area
Glitch Area
VREF- = VEE = -2.5V,VREF+ = +2.5V
MIN
8
-
-
-
-
-
-
-
DC
DC
-
-
-
-
-
-
-
-
-
120
-
-
TYP
MAX
UNITS
- - Bits
- ±1 LSB
-
±0.75
LSB
-
±0.75
LSB
- ±0.5 LSB
-
±0.75
LSB
- ±0.5 LSB
-
±0.25
LSB
50 - MHz
20 - MHz
-2 - ns
8 - ns
5 - ns
5 - ns
25 - ns
25 - ns
22 - ns
4 - ns
20 - ns
160 200
150 - pV/s
250 - pV/s
10-13










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