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NSBA113EDXV6 PDF даташит

Спецификация NSBA113EDXV6 изготовлена ​​​​«ON Semiconductor» и имеет функцию, называемую «Dual PNP Bias Resistor Transistors».

Детали детали

Номер произв NSBA113EDXV6
Описание Dual PNP Bias Resistor Transistors
Производители ON Semiconductor
логотип ON Semiconductor логотип 

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NSBA113EDXV6 Даташит, Описание, Даташиты
MUN5130DW1,
NSBA113EDXV6
Dual PNP Bias Resistor
Transistors
R1 = 1 kW, R2 = 1 kW
PNP Transistors with Monolithic Bias
Resistor Network
This series of digital transistors is designed to replace a single
device and its external resistor bias network. The Bias Resistor
Transistor (BRT) contains a single transistor with a monolithic bias
network consisting of two resistors; a series base resistor and a
base−emitter resistor. The BRT eliminates these individual
components by integrating them into a single device. The use of a BRT
can reduce both system cost and board space.
Features
Simplifies Circuit Design
Reduces Board Space
Reduces Component Count
S and NSV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q101
Qualified and PPAP Capable
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
MAXIMUM RATINGS
(TA = 25°C, common for Q1 and Q2, unless otherwise noted)
Rating
Symbol
Max
Unit
Collector−Base Voltage
VCBO
50
Vdc
Collector−Emitter Voltage
VCEO
50
Vdc
Collector Current − Continuous
IC 100 mAdc
Input Forward Voltage
VIN(fwd)
10
Vdc
Input Reverse Voltage
VIN(rev)
10
Vdc
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
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PIN CONNECTIONS
(3) (2) (1)
R1
Q1
R2 R1
(4) (5)
R2
Q2
(6)
MARKING DIAGRAMS
6
SOT−363
0G M G
CASE 419B
1G
1
0G M G
G
1
SOT−563
CASE 463A
0G = Specific Device Code
M = Date Code*
G = Pb−Free Package
(Note: Microdot may be in either location)
*Date Code orientation may vary depending up-
on manufacturing location.
ORDERING INFORMATION
Device
Package
MUN5130DW1T1G
SOT−363
(Pb−Free)
NSBA113EDXV6T1G SOT−363
(Pb−Free)
Shipping
3000 / Tape &
Reel
4000 / Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2013
November, 2013 − Rev. 2
1
Publication Order Number:
DTA113ED/D









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NSBA113EDXV6 Даташит, Описание, Даташиты
MUN5130DW1, NSBA113EDXV6
THERMAL CHARACTERISTICS
Characteristic
Symbol
MUN5130DW1 (SOT−363) One Junction Heated
Total Device Dissipation
TA = 25°C
(Note 1)
(Note 2)
Derate above 25°C
(Note 2)
(Note 1)
PD
Thermal Resistance,
Junction to Ambient
(Note 1)
(Note 2)
RqJA
MUN5130DW1 (SOT−363) Both Junction Heated (Note 3)
Total Device Dissipation
TA = 25°C
(Note 1)
(Note 2)
Derate above 25°C
(Note 2)
(Note 1)
PD
Thermal Resistance,
Junction to Ambient
(Note 1)
(Note 2)
RqJA
Thermal Resistance,
(Note 1)
Junction to Lead (Note 2)
RqJL
Junction and Storage Temperature Range
NSBA113EDXV6 (SOT−563) One Junction Heated
TJ, Tstg
Total Device Dissipation
TA = 25°C
(Note 1)
Derate above 25°C
(Note 1)
PD
Thermal Resistance,
Junction to Ambient
(Note 1)
RqJA
NSBA113EDXV6 (SOT−563) Both Junction Heated (Note 3)
Total Device Dissipation
TA = 25°C
(Note 1)
Derate above 25°C
(Note 1)
PD
Thermal Resistance,
Junction to Ambient
(Note 1)
RqJA
Junction and Storage Temperature Range
TJ, Tstg
1. FR−4 @ Minimum Pad.
2. FR−4 @ 1.0 x 1.0 Inch Pad.
3. Both junction heated values assume total power is sum of two equally powered channels.
Max Unit
187 mW
256
1.5 mW/°C
2.0
670 °C/W
490
250
385
2.0
3.0
493
325
188
208
−55 to +150
mW
mW/°C
°C/W
°C/W
°C
357 mW
2.9 mW/°C
°C/W
350
500
4.0
250
−55 to +150
mW
mW/°C
°C/W
°C
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NSBA113EDXV6 Даташит, Описание, Даташиты
MUN5130DW1, NSBA113EDXV6
ELECTRICAL CHARACTERISTICS (TA = 25°C, common for Q1 and Q2, unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Collector−Base Cutoff Current
(VCB = 50 V, IE = 0)
ICBO
nAdc
− − 100
Collector−Emitter Cutoff Current
(VCE = 50 V, IB = 0)
ICEO
nAdc
− − 500
Emitter−Base Cutoff Current
(VEB = 6.0 V, IC = 0)
IEBO
mAdc
− − 4.3
Collector−Base Breakdown Voltage
(IC = 10 mA, IE = 0)
V(BR)CBO
50
Vdc
Collector−Emitter Breakdown Voltage (Note 4)
(IC = 2.0 mA, IB = 0)
V(BR)CEO
50
Vdc
ON CHARACTERISTICS
DC Current Gain (Note 4)
(IC = 5.0 mA, VCE = 10 V)
hFE
3.0 5.0
Collector−Emitter Saturation Voltage (Note 4)
(IC = 10 mA, IB = 5.0 mA)
VCE(sat)
− 0.25
Vdc
Input Voltage (off)
(VCE = 5.0 V, IC = 100 mA)
Vi(off)
− 1.3 −
Vdc
Input Voltage (on)
(VCE = 0.2 V, IC = 20 mA)
Vi(on)
− 1.7 −
Vdc
Output Voltage (on)
(VCC = 5.0 V, VB = 2.5 V, RL = 1.0 kW)
Output Voltage (off)
(VCC = 5.0 V, VB = 0.05 V, RL = 1.0 kW)
VOL Vdc
− − 0.2
VOH
4.9 −
Vdc
Input Resistor
R1
0.7 1.0 1.3
kW
Resistor Ratio
R1/R2
0.8 1.0 1.2
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Pulsed Condition: Pulse Width = 300 msec, Duty Cycle 2%.
400
350
300
(1) SOT−363; 1.0 x 1.0 inch Pad
250 (2) SOT−563; Minimum Pad
200
(1) (2)
150
100
50
0
−50 −25
0 25 50 75 100 125 150
AMBIENT TEMPERATURE (°C)
Figure 1. Derating Curve
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