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AD5410 PDF даташит

Спецификация AD5410 изготовлена ​​​​«Analog Devices» и имеет функцию, называемую «Current Source DAC».

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Номер произв AD5410
Описание Current Source DAC
Производители Analog Devices
логотип Analog Devices логотип 

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AD5410 Даташит, Описание, Даташиты
Data Sheet
Single-Channel, 12-/16-Bit, Serial Input, 4 mA to
20 mA, Current Source DAC, HART Connectivity
AD5410/AD5420
FEATURES
12-/16-bit resolution and monotonicity
Current output ranges: 4 mA to 20 mA, 0 mA to 20 mA, or
0 mA to 24 mA
±0.01% FSR typical total unadjusted error (TUE)
±3 ppm/°C typical output drift
Flexible serial digital interface
On-chip output fault detection
On-chip reference (10 ppm/°C maximum)
Feedback/monitoring of output current
Asynchronous clear function
Power supply (AVDD) range
10.8 V to 40 V; AD5410AREZ/AD5420AREZ
10.8 V to 60 V; AD5410ACPZ/AD5420ACPZ
Output loop compliance to AVDD − 2.5 V
Temperature range: −40°C to +85°C
24-lead TSSOP and 40-lead LFCSP packages
APPLICATIONS
Process control
Actuator control
PLC
HART network connectivity
GENERAL DESCRIPTION
The AD5410/AD5420 are low cost, precision, fully integrated
12-/16-bit converters offering a programmable current source
output designed to meet the requirements of industrial process
control applications. The output current range is programmable
at 4 mA to 20 mA, 0 mA to 20 mA, or an overrange function of
0 mA to 24 mA. The output is open-circuit protected. The device
operates with a power supply (AVDD) range from 10.8 V to
60 V. Output loop compliance is 0 V to AVDD − 2.5 V.
The flexible serial interface is SPI, MICROWIRE™, QSPI™, and
DSP compatible and can be operated in 3-wire mode to mini-
mize the digital isolation required in isolated applications.
The device also includes a power-on reset function, ensuring
that the device powers up in a known state, and an asynchronous
CLEAR pin that sets the output to the low end of the selected
current range.
The total unadjusted error is typically ±0.01% FSR.
COMPANION PRODUCTS
HART Modem: AD5700, AD5700-1
DVCC
SELECT
FUNCTIONAL BLOCK DIAGRAM
DVCC
CAP1
CAP2
AV DD
CLEAR
AD5410/AD5420
R3SENSE
R2 R3
BOOST
LATCH
SCLK
SDIN
SDO
INPUT SHIFT
REGISTER
AND CONTROL
LOGIC
12/16
12-/16-BIT
DAC
POWER-
ON
RESET
VREF
RSET
IOUT
FAULT
RSET
REFOUT
REFIN
Figure 1.
GND
Rev. H
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2009–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com









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AD5410 Даташит, Описание, Даташиты
AD5410/AD5420
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Companion Products ....................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
AC Performance Characteristics ................................................ 6
Timing Characteristics ................................................................ 6
Absolute Maximum Ratings............................................................ 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Typical Performance Characteristics ........................................... 11
Terminology .................................................................................... 16
Theory of Operation ...................................................................... 17
Architecture................................................................................. 17
Serial Interface ............................................................................ 17
Power-On State ........................................................................... 20
Transfer Function ....................................................................... 20
Data Register ............................................................................... 20
Control Register.......................................................................... 20
Reset Register.............................................................................. 21
Status Register............................................................................. 21
Data Sheet
AD5410/AD5420 Features ............................................................ 22
Fault Alert.................................................................................... 22
Asynchronous Clear (CLEAR) ................................................. 22
Internal Reference ...................................................................... 22
External Current Setting Resistor ............................................ 22
Digital Power Supply.................................................................. 22
External Boost Function............................................................ 22
HART Communication............................................................. 23
Digital Slew Rate Control.......................................................... 23
IOUT Filtering Capacitors ............................................................ 25
Feedback/Monitoring of Output Current ............................... 25
Applications Information .............................................................. 27
Driving Inductive Loads............................................................ 27
Transient Voltage Protection .................................................... 27
Layout Guidelines....................................................................... 27
Galvanically Isolated Interface ................................................. 27
Microprocessor Interfacing....................................................... 28
Thermal and Supply Considerations ....................................... 28
Industrial, HART Compatible Analog Output Application . 29
Outline Dimensions ....................................................................... 30
Ordering Guide .......................................................................... 30
Rev. H | Page 2 of 30









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AD5410 Даташит, Описание, Даташиты
Data Sheet
REVISION HISTORY
4/15—Rev. G to Rev. H
Changes to Table 3 ............................................................................6
Changes to Table 5 ............................................................................9
10/14—Rev. F to Rev. G
Changes to Power-On State Section .............................................20
10/13—Rev. E to Rev. F
Moved Revision History...................................................................3
Changes to Figure 51 ......................................................................27
Changes to Figure 55 ......................................................................29
3/13—Rev. D to Rev. E
Changes to Table 4 ............................................................................7
Added Figure 40, Renumbered Sequentially ...............................19
Changes to Table 10 ........................................................................20
Changes to Thermal and Supply Considerations Section
and Table 21 .....................................................................................27
Updated Outline Dimensions........................................................29
5/12—Rev. C to Rev. D
Reorganized Layout ........................................................... Universal
Changes to Product Title..................................................................1
Added Companion Products Section; Changes to Features
Section and Applications Section....................................................1
Changes to Table 5 ............................................................................9
Change to Figure 8 ..........................................................................11
Added HART Communication Section and Figure 41,
Renumbered Sequentially ..............................................................21
Changes to Industrial, HART Compatible Analog Output
Application Section and Figure 54................................................27
AD5410/AD5420
11/11—Rev. B to Rev. C
Changes to Table 10 ........................................................................18
2/10—Rev. A to Rev. B
Changes to Figure 46 .....................................................................23
8/09—Rev. 0 to Rev. A
Changes to Features and General Description .............................1
Changes to Table 1 ............................................................................3
Changes to Table 2 ............................................................................5
Changes to Introduction to Table 4 and to Table 4 ......................7
Added Figure 6, Changes to Figure 5 and Table 5 ........................8
Added Feedback/Monitoring of Output Current Section,
Including Figure 45 to Figure 47; Renumbered Subsequent
Figures ..............................................................................................23
Changes to Thermal and Supply Considerations Section and
Table 21.............................................................................................26
Updated Outline Dimensions........................................................28
Changes to Ordering Guide...........................................................28
3/09—Revision 0: Initial Version
Rev. H | Page 3 of 30










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