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CAT1163P-28TE13 PDF даташит

Спецификация CAT1163P-28TE13 изготовлена ​​​​«Catalyst Semiconductor» и имеет функцию, называемую «Supervisory Circuit with I2C Serial CMOS EEPROM/ Precision Reset Controller and Watchdog Timer».

Детали детали

Номер произв CAT1163P-28TE13
Описание Supervisory Circuit with I2C Serial CMOS EEPROM/ Precision Reset Controller and Watchdog Timer
Производители Catalyst Semiconductor
логотип Catalyst Semiconductor логотип 

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CAT1163P-28TE13 Даташит, Описание, Даташиты
CAT1163 (16K)
Supervisory Circuit with I2C Serial CMOS EEPROM, Precision Reset Controller and Watchdog Timer
FEATURES
s Watchdog timer input (WDI)
s 400kHz I2C bus compatible
s 2.7V to 6.0V operation
s Low power CMOS technology
s 16-Byte page write buffer
s Built-in inadvertent write protection
— V lock out
CC
— Write protect pin, WP
s Active high or low reset
— Precision power supply voltage monitor
— 5V, 3.3V and 3V systems
— Five threshold voltage options
s 1,000,000 Program/Erase cycles
s Manual reset
s 100 Year data retention
s 8-pin DIP or 8-pin SOIC
s Commercial and industrial temperature ranges
DESCRIPTION
The CAT1163 is a complete memory and supervisory
solution for microcontroller-based systems. A serial
EEPROM memory (16K) with hardware memory write
protection, a system power supervisor with brown out
protection and a watchdog timer are integrated together
in low power CMOS technology. Memory interface is via
an I2C bus.
supply voltages are out of tolerance reset signals become
active, preventing the system microcontroller, ASIC or
peripherals from operating. Reset signals become inactive
typically 200 ms after the supply voltage exceeds the reset
threshold level. With both active high and low reset signals,
interface to microcontrollers and other ICs is simple. In
addition, a reset pin can be used as debounced input for
push-button manual reset capability.
The 1.6-second watchdog circuit returns a system to a
known good state if a software or hardware glitch halts
or “hangs” the system. The CAT1163 watchdog monitors
the WDI input pin.
The power supply monitor and reset circuit protects
memory and system controllers during power up/down
and against brownout conditions. Five reset threshold
voltages support 5V, 3.3V and 3V systems. If power
The CAT1163 memory features a 16-byte page. In addition,
hardware data protection is provided by a write protect pin
WP and by a VCC sense circuit that prevents writes to
memory whenever VCC falls below the reset threshold or
until VCC reaches the reset threshold during power up.
Available packages include an 8-pin DIP and a surface
mount, 8-pin SO package.
PIN CONFIGURATION
WDI
RESET
WP
GND
CAT1163
VCC
RESET
SCL
SDA
Reset Threshold Voltage Options
Part Dash Minimum Maximum
Number Threshold Threshold
-45 4.50 4.75
-42 4.25 4.50
-30 3.00 3.15
-28 2.85 3.00
-25 2.55 2.70
© 2002 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
BLOCK DIAGRAM
EXTERNAL LOAD
VCC
GND
DOUT
ACK
WORD ADDRESS
BUFFERS
SENSE AMPS
SHIFT REGISTERS
COLUMN
DECODERS
SDA
START/STOP
LOGIC
XDEC
EEPROM
CONTROL
WP LOGIC
RESET Controller
Precision
WATCHDOG
Vcc Monitor
DATA IN STORAGE
HIGH VOLTAGE/
TIMING CONTROL
STATE COUNTERS
SLAVE
ADDRESS
COMPARATORS
SCL
WDI RESET RESET
Doc No. 3003, Rev. C









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CAT1163P-28TE13 Даташит, Описание, Даташиты
CAT1163
ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature ....................... –65°C to +150°C
Voltage on any Pin with
Respect to Ground(1) ............ –2.0V to +VCC +2.0V
VCC with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (TA = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100 mA
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica-
tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
mance and reliability.
PIN FUNCTIONS
Pin No. Pin Name
1 WDI
2 RESET
3 WP
4 GND
5 SDA
6 SCL
7 RESET
8 VCC
Function
Watchdog Timer Input
Active Low Reset I/O
Write Protect
Ground
Serial Data/Address
Clock Input
Active High Reset I/O
Power Supply
RELIABILITY CHARACTERISTICS
Symbol
NEND(3)
TDR(3)
VZAP(3)
ILTH(3)(4)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-Up
Reference Test Method
Min
MIL-STD-883, Test Method 1033 1,000,000
MIL-STD-883, Test Method 1008 100
MIL-STD-883, Test Method 3015 2000
JEDEC Standard 17
100
Max
Units
Cycles/Byte
Years
Volts
mA
DC OPERATING CHARACTERISTICS
VCC = +2.7V to +6.0V, unless otherwise specified.
Symbol Parameter
Test Conditions
Min
ICC Power Supply Current
fSCL = 100 kHz
ISB Standby Current
VCC = 3.3V
VCC = 5
ILI
Input Leakage Current
VIN = GND or VCC
ILO
Output Leakage Current
VIN = GND or VCC
VIL Input Low Voltage
-1
VIH Input High Voltage
VCC x 0.7
VOL1
Output Low Voltage (SDA) IOL = 3 mA, VCC = 3.0V
Typ Max Units
3 mA
40 µA
50 µA
2 µA
10 µA
VCC x 0.3
V
VCC + 0.5
V
0.4 V
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.
Doc. No. 3003, Rev. C
2









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CAT1163P-28TE13 Даташит, Описание, Даташиты
CAT1163
CAPACITANCE
TA = 25˚C, f = 1.0 MHz, VCC = 5V
Symbol Test
CI/O(1)
Input/Output Capacitance (SDA)
CIN(1)
Input Capacitance (SCL)
AC CHARACTERISTICS
VCC=2.7V to 6.0V unless otherwise specified.
Output Load is 1 TTL Gate and 100pF.
SYMBOL PARAMETER
FSCL
TI(1)
Clock Frequency
Noise Suppresion Time
Constant at SCL, SDA Inputs
tAA
tBUF(1)
SLC Low to SDA Data Out
and ACK Out
Time the Bus Must be Free Before
a New Transmission Can Start
tHD:STA Start Condition Hold Time
tLOW
Clock Low Period
tHIGH
tSU:STA
Clock High Period
Start Condition Setup Time
(for a Repeated Start Condition)
tHD:DAT Data in Hold Time
tSU:DAT
tR(1)
tF(1)
Data in Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
tSU:STO Stop Condition Setup Time
tDH Data Out Hold Time
Max
8
6
Units
pF
pF
Conditions
VI/O = 0V
VIN = 0V
VCC = 2.7V - 6V
Min Max
100
200
3.5
4.7
4
4.7
4
4.7
0
50
1
300
4
100
VCC = 4.5V - 5.5V
Min Max
400
200
1
1.2
0.6
1.2
0.6
0.6
0
50
0.3
300
0.6
100
Units
kHz
ns
µs
µs
µs
µs
µs
µs
ns
ns
µs
ns
µs
ns
POWER-UP TIMING (1)(2)
Symbol Parameter
tPUR Power-up to Read Operation
tPUW
Power-up to Write Operation
Max Units
1 ms
1 ms
WRITE CYCLE LIMITS
Symbol Parameter
Min Typ
Max Units
tWR Write Cycle Time
10 ms
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the
write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.
NOTE:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) tPUR and tPUW are the delays required from the time VCC is stable until the specific operation can be initiated.
3 Doc No. 3003, Rev. C










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