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PDF HMC1119 Data sheet ( Hoja de datos )
| Número de pieza | HMC1119 | |
| Descripción | Silicon Digital Attenuator | |
| Fabricantes | Analog Devices | |
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Data Sheet
0.25 dB LSB, 7-Bit, Silicon Digital
Attenuator, 0.1 GHz to 6.0 GHz
HMC1119
FEATURES
Attenuation range: 0.25 dB LSB steps to 31.75 dB
Low insertion loss:
1.1 dB at 1.0 GHz
1.3 dB at 2.0 GHz
Typical step error: less than ±0.1 dB
Excellent attenuation accuracy: less than ±0.2 dB
Low phase shift error: 6° phase shift at 1.0 GHz
Safe state transitions
High linearity
1 dB compression (P1dB): 31 dBm typical
Input third-order intercept (IP3): 54 dBm typical
RF settling time (0.05 dB final RF output): 250 ns
Single supply operation: 3.3 V to 5.0 V
ESD rating: Class 2 (2 kV human body model (HBM))
24-lead, 4 mm × 4 mm LFCSP package: 16 mm2
APPLICATIONS
Cellular infrastructure
Microwave radios and very small aperture terminals (VSATs)
Test equipment and sensors
IF and RF designs
GENERAL DESCRIPTION
The HMC1119 is a broadband, highly accurate, 7-bit digital
attenuator, operating from 0.1 GHz to 6.0 GHz with 31.5 dB
attenuation control range in 0.25 dB steps.
The HMC1119 is implemented in a silicon process, offering
very fast settling time, low power consumption, and high ESD
robustness. The device features safe state transitions and is
optimized for excellent step accuracy and high linearity over
frequency and temperature range. The RF input and output are
internally matched to 50 Ω and do not require any external
matching components. The design is bidirectional; therefore,
the RF input and output are interchangeable.
FUNCTIONAL BLOCK DIAGRAM
24 23 22 21 20 19
D0 1
18 SERNIN
VDD 2
P/S 3
SERIAL/
PARALLEL
CONTROL
17 CLK
16 LE
GND 4
ATTNIN 5
GND 6
7
7-BIT
DIGITAL
ATTENUATOR
15 GND
14 ATTNOUT
13 GND
8 9 10 11 12
PACKAGE
BASE
GND
Figure 1.
The HMC1119 has an on-chip regulator that can support a wide
supply operating range from 3.3 V to 5.0 V with no performance
change in electrical characteristics. The HMC1119 incorporates a
driver that supports serial (3-wire) and parallel controls of the
attenuator.
The HMC1119 comes in a RoHS-compliant, compact, 4 mm ×
4 mm LFCSP package.
A fully populated evaluation board is available.
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
HMC1119
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
RF Input Power (TCASE = 85°C)
Digital Control Inputs (P/S, CLK,
SERNIN, LE, D0 to D6)
Supply Voltage (VDD)
Continuous Power Dissipation (PDISS)
Thermal Resistance (at Maximum
Power Dissipation)
Temperature
Channel Temperature
Storage
Maximum Reflow Temperature
ESD Sensitivity (HBM)
Rating
25 dBm
−0.3 V to VDD + 0.5 V
−0.3 V to +5.5 V
0.31 W
156°C/W
135°C
−65°C to +150°C
260°C (MSL3 Rating)
2 kV (Class 2)
Data Sheet
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
Rev. 0 | Page 4 of 15
5 Page 
HMC1119
THEORY OF OPERATION
The HMC1119 incorporates a 7-bit fixed attenuator array that
offers an attenuation range of 0.25 dB to 31.75 dB, with 0.25 dB
steps. An integrated driver provides both serial and parallel
mode control of the attenuator array (see Figure 22).
The HMC1119 can be in either serial or parallel mode control
by setting the P/S pin to high or low, respectively (see Table 4). The
7-bit data, loaded in either serial or parallel mode, then latches with
the control signal, LE, to determine the attenuator value.
Table 4. Mode Selection Table1
P/S Pin State
Control Mode
Low Parallel
High
Serial
1 The P/S pin must always be kept at a valid logic level (VIH or VIL) and must not
be left floating.
SERIAL CONTROL INTERFACE
The HMC1119 utilizes a 3-wire serial to parallel (SPI)
configuration, as shown in the serial mode timing diagram (see
Figure 23): serial data input (SERIN), clock (CLK), and latch
enable (LE). The serial control interface activates when the
P/S pin is set to high.
In serial mode, the 7-bit SERIN data is clocked MSB first on rising
CLK edges into the shift register; then, LE must be toggled high
to latch the new attenuation state into the device. The LE must
be set low to clock a set of 7-bit data into the shift register because
CLK is masked to prevent the attenuator value from changing if LE
is kept high.
In serial mode operation, both the serial control inputs (LE, CLK,
SERNIN) and the parallel control inputs (D0 to D6) must always be
kept at a valid logic level (VIH or VIL) and must not be left floating. It
is recommended to connect the parallel control inputs to ground
and to use pull-down resistors on all serial control input lines
if the device driving these input lines goes high impedance
during hibernation.
PARALLEL CONTROL INTERFACE
The parallel control interface has seven digital control input lines
(D6 to D0) to set the attenuation value. D6 is the most significant
bit (MSB) that selects the 16 dB attenuator stage, and D0 is the
least significant bit (LSB) that selects the 0.25 dB attenuator stage
(see Figure 22).
In parallel mode operation, both the serial control inputs (LE, CLK,
SERNIN) and the parallel control inputs (D0 to D6) must always be
Data Sheet
kept at a valid logic level (VIH or VIL) and must not be left floating.
It is recommended to connect the serial control inputs to ground
and to use pull-down resistors on all parallel control input lines
if the device driving these input lines goes high impedance
during hibernation.
Setting P/S to low enables parallel mode. There are two modes of
parallel operation: direct parallel mode and latched parallel mode.
Direct Parallel Mode
For direct parallel mode, the latch enable (LE) pin must be kept
high. Change the attenuation state using the control voltage inputs
(D0 to D6) directly. This mode is ideal for manual control of the
attenuator and using hardware, switches, or a jumper.
Latched Parallel Mode
The latch enable (LE) pin must be low when changing the
control voltage inputs (D0 to D6) to set the attenuation state.
When the desired state is set, LE must be toggled high to transfer
the 7-bit data to the bypass switches of the attenuator array, then
toggled low to latch the change into the device (see Figure 24).
RF INPUT OUTPUT
The attenuator in the HMC1119 is bidirectional; the ATTNIN
and ATTNOUT pins are interchangeable as the RF input and
output ports. The attenuator is internally matched to 50 Ω at both
input and output; therefore, no external matching components
are required. The RF pins are dc-coupled; therefore, dc blocking
capacitors are required on RF lines.
POWER-UP SEQUENCE
The ideal power-up sequence is as follows:
1. Power up GND.
2. Power up VDD.
3. Power up the digital control inputs (the relative order of
the digital control inputs is not important).
4. Power up the RF input.
For latched parallel mode operation, LE must be toggled. The
relative order of the digital inputs is not important as long as the
inputs are powered up after GND and VDD.
Power-Up States
The logic state of the device is at maximum attenuation when, at
power up, LE is set to low. The attenuator latches in the desired
power-up state approximately 200 ms after power up.
Rev. 0 | Page 10 of 15
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet HMC1119.PDF ] | |
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