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CAT24C023 PDF даташит

Спецификация CAT24C023 изготовлена ​​​​«Catalyst Semiconductor» и имеет функцию, называемую «Supervisory Circuits with I2C Serial CMOS E2PROM/ Precision Reset Controller and Watchdog Timer».

Детали детали

Номер произв CAT24C023
Описание Supervisory Circuits with I2C Serial CMOS E2PROM/ Precision Reset Controller and Watchdog Timer
Производители Catalyst Semiconductor
логотип Catalyst Semiconductor логотип 

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CAT24C023 Даташит, Описание, Даташиты
Advanced
CAT24C163(16K), CAT24C083(8K)
CAT24C043(4K), CAT24C023(2K)
Supervisory Circuits with I2C Serial CMOS E2PROM, Precision Reset Controller and Watchdog Timer
FEATURES
s Watchdog Timer Input (WDI)
s Programmable Reset Threshold
s 400 KHz I2C Bus Compatible
s 2.7 to 6 Volt Operation
s Low Power CMOS Technology
s 16 - Byte Page Write Buffer
s Built-in inadvertent write protection
— VCC Lock Out
DESCRIPTION
s Active High or Low Reset Outputs
— Precision Power Supply Voltage Monitoring
— 5V, 3.3V and 3V options
s 1,000,000 Program/Erase Cycles
s 100 Year Data Retention
s 8-Pin DIP or 8-Pin SOIC
s Commercial, Industrial and Automotive
Temperature Ranges
The CAT24CXX3 is a single chip solution to three
popular functions of EEPROM memory, precision reset
controller and watchdog timer. The 24C163(16K),
24C083(8K), 24C043(4K) and 24C023(2K) feature a I2C
Serial CMOS EEPROM Catalyst advanced CMOS tech-
nology substantially reduces device power requirements.
The 24CXX3 features a 16-byte page and is available in
8-pin DIP or 8-pin SOIC packages.
The reset function of the 24CXX3 protects the system
during brown out and power up/down conditions. During
system failure the watchdog timer feature protects the
microcontroller with a reset signal. 24CXX3 features
active low reset on pin 2 and active high reset on pin 7.
24CXX3 features watchdog timer on the WDI input pin
(pin 1).
PIN CONFIGURATION
24CXX3
WDI
RESET
WP
VSS
VCC
RESET
SCL
SDA
BLOCK DIAGRAM
EXTERNAL LOAD
VCC
VSS
DOUT
ACK
WORD ADDRESS
BUFFERS
SENSE AMPS
SHIFT REGISTERS
COLUMN
DECODERS
*All products offered in P and J packages
PIN FUNCTIONS
Pin Name
Function
SDA
Serial Data/Address
RESET/RESET Reset I/O
SCL Clock Input
Vcc Power Supply
VSS Ground
WDI Watchdog Timer Input
WP Write Protect
SDA
WP
START/STOP
LOGIC
CONTROL
LOGIC
XDEC
E2PROM
RESET Controller
High
Precision
WATCHDOG
Vcc Monitor
DATA IN STORAGE
HIGH VOLTAGE/
TIMING CONTROL
STATE COUNTERS
SLAVE
ADDRESS
COMPARATORS
SCL
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
WDI RESET/RESET
1
24C1601 BLOCK
Doc. No. 25080-00 3/98 M-1









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CAT24C023 Даташит, Описание, Даташиты
CAT24C163/083/043/023
Advanced
ABSOLUTE MAXIMUM RATINGS*
COMMENT
Temperature Under Bias....................–55°C to +125°C
Storage Temperature........................ –65°C to +150°C
Voltage on Any Pin with
Respect to Ground(1) ..............–2.0V to +VCC + 2.0V
VCC with Respect to Ground..................–2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C)1.0W.................................1.0W
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica-
tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
mance and reliability.
Lead Soldering Temperature (10 secs)...............300°C
Output Short Circuit Current(2) ..........................100mA
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Min.
Max. Units
Reference Test Method
NEND(3)
TDR(3)
VZAP(3)
ILTH(3)(4)
Endurance
Data Retention
ESD Susceptibility
Latch-up
1,000,000
100
2000
100
D.C. OPERATING CHARACTERISTICS
VCC = +2.7V to +6.0V, unless otherwise specified.
Symbol Parameter
Min.
Cycles/Byte
Years
Volts
mA
Limits
Typ. Max.
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
Units
Test Conditions
ICC Power Supply Current
Isb Standby Current
3 mA fSCL = 100 KHz
40 µA Vcc=3.3V
50 µA Vcc=5
ILI
ILO
VIL
VIH
VOL
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage (SDA)
–1
VCC x 0.7
2 µA
10 µA
VCC x 0.3 V
VCC + 0.5 V
0.4 V
VIN=GND or VCC
VIN=GND or VCC
IOL = 3 mA, VCC = 3.0V
CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V
Symbol Test
Max.
Units
Conditions
CI/O(3)
Input/Output Capacitance (SDA)
8
pF
VI/O = 0V
CIN(3)
Input Capacitance (SCL)
6 pF
VIN = 0V
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.
Doc. No. 25080-00 3/98 M-1
2









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CAT24C023 Даташит, Описание, Даташиты
Advanced
CAT24C163/083/043/023
A.C. CHARACTERISTICS
VCC=2.7V to 6.0V unless otherwise specified.
Output Load is 1 TTL Gate and 100pF
Read & Write Cycle Limits
Symbol
Parameter
FSCL
TI(1)
tAA
tBUF(1)
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR(1)
tF(1)
tSU:STO
tDH
Clock Frequency
Noise Suppression Time
Constant at SCL, SDA Inputs
SCL Low to SDA Data Out
and ACK Out
Time the Bus Must be Free Before
a New Transmission Can Start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time
(for a Repeated Start Condition)
Data In Hold Time
Data In Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
VCC=2.7V - 6V
Min. Max.
100
200
3.5
4.7
4
4.7
4
4.7
0
50
1
300
4
100
VCC=4.5V - 5.5V
Min.
Max.
400
200
1
1.2
0.6
1.2
0.6
0.6
0
50
0.3
300
0.6
100
Units
kHz
ns
µs
µs
µs
µs
µs
µs
ns
ns
µs
ns
µs
ns
Power-Up Timing(1)(2)
Symbol
Parameter
Max.
tPUR Power-up to Read Operation
1
tPUW
Power-up to Write Operation
1
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
Write Cycle Limits
Symbol
Parameter
Min.
Typ.
Max
tWR Write Cycle Time
10
Units
ms
ms
Units
ms
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase
cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device
does not respond to its slave address.
3 Doc. No. 25080-00 3/98 M-1










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