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PDF HMC834LP6GE Data sheet ( Hoja de datos )
| Número de pieza | HMC834LP6GE | |
| Descripción | Fractional-N PLL | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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HMC834LP6GE
v01.0112
Fractional-N PLL with Integrated VCO
45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 MHz
Features
• RF Bandwidth:
45 - 1050, 1400 - 2100, 2800 - 4200, 5600
- 8400 MHz
• Maximum Phase Detector Rate
100 MHz
• Ultra Low Phase Noise
-110 dBc/Hz in Band Typ.
• Figure of Merit (FOM) -227 dBc/Hz
• <180 fs RMS Jitter
• 24-bit Step Size, Resolution 3 Hz typ
• Exact Frequency Mode
• Built in Digital Self Test
• 40 Lead 6x6 mm SMT Package: 36 mm2
Typical Applications
• Cellular/4G, WiMax Infrastructure
• Repeaters and Femtocells
• Communications Test Equipment
• CATV Equipment
Functional Diagram
• Phased Array Applications
• DDS Replacement
• Very High Data Rate Radios
• Tunable Reference Source for Spurious-
Free Performance
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1 page  
HMC834LP6GE
v01.0112
Fractional-N PLL with Integrated VCO
45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 MHz
Electrical Specifications (Continued)
Parameter
Condition
+5 V VCO Core and VCO Buffer
fo/1 Mode VCC2
fo/N Mode VCC2
Single-Ended Output Mode
fo/1 Mode VCC1
+5 V VCO Divider and RF/PLL Buffer
Differential Output Mode
fo/1 Mode VCC1
Single-Ended Output Mode
fo/N Mode VCC1
Differential Output Mode
fo/N Mode VCC1
+3.3 V
AVDD, VCCHF, VCCPS,
VCCPD, RVDD, DVDD3V
Power Down - Crystal Off
Reg 01h=0,
Crystal Not Clocked
Power Down - Crystal On, 100 MHz
Reg01h =0,
Crystal Clocked 100 MHz
Power on Reset
Typical Reset Voltage on DVDD
Min DVDD Voltage for No Reset
Power on Reset Delay
VCO Open Loop Phase Noise at fo @ 4 GHz
10 kHz Offset
100 kHz Offset
1 MHz Offset
10 MHz Offset
100 MHz Offset
VCO Open Loop Phase Noise at fo @ 4 GHz/2 = 2 GHz
10 kHz Offset
100 kHz Offset
1 MHz Offset
10 MHz Offset
100 MHz Offset
VCO Open Loop Phase Noise at fo @ 2.8 GHz/28 = 100 MHz
10 kHz Offset
100 kHz Offset
1 MHz Offset
10 MHz Offset
100 MHz Offset
VCO Open Loop Phase Noise at 2fo @ 5.6 GHz
10 kHz Offset
100 kHz Offset
1 MHz Offset
10 MHz Offset
100 MHz Offset
Min.
80
95
1.5
Typ.
105
80
25
40
52
10
5
700
250
-78
-108
-134.5
-156
-171
-83
-113
-139.5
-165.5
-167
-111
-141
-163.5
-170
-173
-77
-107
-132
-154
-162
Max.
100
115
Units
mA
mA
mA
mA
mA
mA
mA
µA
mA
mV
V
µs
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
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4
5 Page 
Pin Descriptions
Pin Number
1
2, 5, 6, 8, 9,
11 - 14, 18 - 22, 24,
26, 29, 34, 37, 38
3
4
7
10
15
16
17
23
25
27
28
30
31
32
33
35
36
39
40
HMC834LP6GE
v01.0112
Fractional-N PLL with Integrated VCO
45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 MHz
Function
AVDD
N/C
VPPCP
CP
VDDLS
RVDD
XREFP
DVDD3V
CEN
VTUNE
VCC2
VCC1
RF_N
SEN
SDI
SCK
LD_SDO
VCCHF
VCCPS
VCCPD
BIAS
Description
DC Power Supply for analog circuitry.
The pins are not connected internally; however, all data shown herein
was measured with these pins connected to RF/DC ground externally.
Power Supply for charge pump analog section
Charge Pump Output
Power Supply for the charge pump digital section
Reference Supply
Reference Oscillator Input
DC Power Supply for Digital (CMOS) Circuitry
Chip Enable. Connect to logic high for normal operation.
VCO Varactor. Tuning Port Input.
VCO Analog Supply 2
VCO Analog Supply 1
RF Negative Output (On in differential and single-ended configuration)
PLL Serial Port Enable (CMOS) Logic Input
PLL Serial Port Data (CMOS) Logic Input
PLL Serial Port Clock (CMOS) Logic Input
Lock Detect, or Serial Data, or General Purpose (CMOS) Logic Output (GPO)
DC Power Supply for Analog Circuitry
DC Power Supply for Analog Prescaler
DC Power Supply for Phase Detector
External bypass decoupling for precision bias circuits.
Note: 1.920V ±20mV reference voltage (BIAS) is generated internally and cannot
drive an external load. Must be measured with 10GΩ meter such as Agilent 34410A,
normal 10MΩ DVM will read erroneously.
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10
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HMC834LP6GE.PDF ] | |
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