NJU26904 PDF даташит
Спецификация NJU26904 изготовлена «New Japan Radio» и имеет функцию, называемую «Digital Audio Delay». |
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Детали детали
Номер произв | NJU26904 |
Описание | Digital Audio Delay |
Производители | New Japan Radio |
логотип |
18 Pages
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NJU26904
Digital Audio Delay
■ General Description
The NJU26904 offers digital audio delay.
The NJU26904 has internal delay memory. Delay function can adjust output
time of a six-channel signal.
This delay functions are suitable for delay time adjustment such as Audio
products and time alignment such as Car Audio.
■Package
■ FEATURES
NJU26904V-C2
• 6-channel Digital Audio Delay
Delay Time 84msec for monaural channel, 42msec for stereo channel at Fs=96kHz
Delay Time 169msec for monaural channel, 85msec for stereo channel at Fs=48kHz
Delay Time 254msec for monaural channel, 127msec for stereo channel at Fs=32kHz
• Delay data width is 24 bits.
Digital Audio Format: I2S 24bit, Left-Justified, Right-Justified, BCK: 32/64fs
• Adjustable Delay Time with 1sample units for 8,121 samples at maximum.
• Selectable input sources for each channel output freely.
• To make long delay time, the NJU26904 can be connected serially.
• Non-Audio Format is possible.
- Hardware
• Maximum System Clock Frequency : 12.288MHz Max. built-in PLL Circuit
• Digital Audio Interface
: 3 Input ports / 3 Output ports
• Digital Audio Format
: I2S 24bit, Left- Justified, Right-Justified, BCK : 32/64fs
• Master / Slave Mode
- Master Mode, MCK : 384fs @32kHz, 256fs @48kHz
• Host Interface
: I2C bus (Fast-mode/400kbps)
• Power Supply
: 3.3V
• Input terminal
: 5V Input tolerant
• Package
: SSOP24-C2 (Pb-Free)
Ver.2008-12-02
-1-
No Preview Available ! |
NJU26904
■ Function Block Diagram
SCL
SDA
I2C INTERFACE
RESETb
MCK
CLKOUT
CLK
SLAVEb
TIMING
GENERATOR /
PLL
Internal Pow er
(1.8V)
VREGO
External
Low -ESR
Capacitors
Required
Built-in LDO
1.8V level terminal
HOST CONTROL
ADDRESS GENERATION UNIT
Delay RAM
SERIAL AUDIO
INTERFACE
GPIO
INTERFACE
Fig. 1 NJU26904 Block Diagram
SDI0-2
SDO0-2
BCK
LR
WDC
AD2
AD1
-2-
Ver.2008-12-02
No Preview Available ! |
■ DSP Block Diagram
SDI0_L
SDI0_R
SDI1_L
SDI1_R
SDI2_L
SDI2_R
SDI0_L
SDI0_R
SDI1_L
SDI1_R
SDI2_L
SDI2_R
SDI0_L
SDI0_R
SDI1_L
SDI1_R
SDI2_L
SDI2_R
SDI0_L
SDI0_R
SDI1_L
SDI1_R
SDI2_L
SDI2_R
SDI0_L
SDI0_R
SDI1_L
SDI1_R
SDI2_L
SDI2_R
SDI0_L
SDI0_R
SDI1_L
SDI1_R
SDI2_L
SDI2_R
SDO0_L
SDO0_R
Delay Memory
Free dividing
SDO1_L
SDO1_R
SDO2_L
SDO2_R
Fig. 2 NJU26904 Function Diagram
NJU26904
Ver.2008-12-02
-3-
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