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CAT24WC65 PDF даташит

Спецификация CAT24WC65 изготовлена ​​​​«Catalyst Semiconductor» и имеет функцию, называемую «32K/64K-Bit I2C Serial CMOS E2PROM».

Детали детали

Номер произв CAT24WC65
Описание 32K/64K-Bit I2C Serial CMOS E2PROM
Производители Catalyst Semiconductor
логотип Catalyst Semiconductor логотип 

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CAT24WC65 Даташит, Описание, Даташиты
Preliminary
CAT24WC33/65
32K/64K-Bit I2C Serial CMOS E2PROM
FEATURES
s 400 KHz I2C Bus Compatible*
s 1.8 to 6 Volt Read and Write Operation
s Cascadable for up to Eight Devices
s 32-Byte Page Write Buffer
s Self-Timed Write Cycle with Auto-Clear
s 8-Pin DIP or 8-Pin SOIC
s Schmitt Trigger Inputs for Noise Protection
DESCRIPTION
The CAT24WC33/65 is a 32K/64K-bit Serial CMOS
E2PROM internally organized as 4096/8192 words of 8
bits each. Catalyst’s advanced CMOS technology sub-
stantially reduces device power requirements. The
s Zero Standby Current
s Commercial, Industrial and Automotive Tem-
perature Ranges
s Write Protection
–Bottom 1/4 Array Protected When WP at VIH
s 1,000,000 Program/Erase Cycles
s 100 Year Data Retention
CAT24WC33/65 features a 32-byte page write buffer.
The device operates via the I2C bus serial interface and
is available in 8-pin DIP or 8-pin SOIC packages.
PIN CONFIGURATION
DIP Package (P)
A0
A1
A2
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
BLOCK DIAGRAM
EXTERNAL LOAD
VCC
VSS
DOUT
ACK
WORD ADDRESS
BUFFERS
SENSE AMPS
SHIFT REGISTERS
COLUMN
DECODERS
SOIC Package (J,K)
A0
A1
A2
VSS
1
2
3
4
PIN FUNCTIONS
8 VCC
7 WP
6 SCL
5 SDA
24WC33/65 F01
SDA
WP
START/STOP
LOGIC
CONTROL
LOGIC
256
E2PROM
XDEC 128/256 128/256 X 256
Pin Name
Function
A0, A1, A2 Device Address Inputs
DATA IN STORAGE
SDA
SCL
Serial Data/Address
Serial Clock
HIGH VOLTAGE/
TIMING CONTROL
WP Write Protect
VCC +1.8V to +6V Power Supply
VSS Ground
SCL
A0
A1
A2
STATE COUNTERS
SLAVE
ADDRESS
COMPARATORS
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
24WC33/65 F02
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 25064-00 2/98 S-1









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CAT24WC65 Даташит, Описание, Даташиты
CAT24WC33/65
Preliminary
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature ....................... –65°C to +150°C
Voltage on Any Pin with
Respect to Ground(1) ........... –2.0V to +VCC + 2.0V
VCC with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100mA
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Min.
NEND(3)
TDR(3)
VZAP(3)
ILTH(3)(4)
Endurance
Data Retention
ESD Susceptibility
Latch-up
1,000,000
100
2000
100
Max.
Units
Cycles/Byte
Years
Volts
mA
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
D.C. OPERATING CHARACTERISTICS
VCC = +1.8V to +6.0V, unless otherwise specified.
Limits
Symbol Parameter
Min. Typ. Max.
ICC
ISB(5)
ILI
ILO
VIL
VIH
VOL1
VOL2
Power Supply Current
Standby Current (VCC = 5V)
Input Leakage Current
Output Leakage Current
Input Low Voltage
–1
Input High Voltage
VCC x 0.7
Output Low Voltage (VCC = +3.0V)
Output Low Voltage (VCC = +1.8V)
3
0
10
10
VCC x 0.3
VCC + 0.5
0.4
0.5
Units
mA
µA
µA
µA
V
V
V
V
Test Conditions
fSCL = 100 KHz
VIN = GND or VCC
VIN = GND to VCC
VOUT = GND to VCC
IOL = 3.0 mA
IOL = 1.5 mA
CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V
Symbol
Test
CI/O(3) Input/Output Capacitance (SDA)
CIN(3) Input Capacitance (A0, A1, A2, SCL, WP)
Max.
8
6
Units
pF
pF
Conditions
VI/O = 0V
VIN = 0V
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.
(5) Standby current (ISB ) = 0 µA (<900 nA).
Doc. No. 25064-00 2/98 S-1
2









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CAT24WC65 Даташит, Описание, Даташиты
Preliminary
CAT24WC33/65
A.C. CHARACTERISTICS
VCC = +1.8V to +6V, unless otherwise specified
Output Load is 1 TTL Gate and 100pF
Read & Write Cycle Limits
Symbol
Parameter
FSCL
TI(1)
tAA
tBUF(1)
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR(1)
tF(1)
tSU:STO
tDH
Clock Frequency
Noise Suppression Time
Constant at SCL, SDA Inputs
SCL Low to SDA Data Out
and ACK Out
Time the Bus Must be Free Before
a New Transmission Can Start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time
(for a Repeated Start Condition)
Data In Hold Time
Data In Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
1.8V, 2.5V
Min. Max.
100
200
3.5
4.7
4
4.7
4
4.7
0
50
1
300
4
100
4.5V-5.5V
Min.
Max.
400
200
1
1.2
0.6
1.2
0.6
0.6
0
50
0.3
300
0.6
100
Units
kHz
ns
µs
µs
µs
µs
µs
µs
ns
ns
µs
ns
µs
ns
Power-Up Timing (1)(2)
Symbol
Parameter
tPUR Power-Up to Read Operation
tPUW
Power-Up to Write Operation
Max.
1
1
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
Write Cycle Limits
Symbol
Parameter
tWR Write Cycle Time
Min.
Typ.
Max
10
Units
ms
ms
Units
ms
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
address.
3 Doc. No. 25064-00 2/98 S-1










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