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CAT25C256 PDF даташит

Спецификация CAT25C256 изготовлена ​​​​«Catalyst Semiconductor» и имеет функцию, называемую «128K/256K-Bit SPI Serial CMOS E2PROM».

Детали детали

Номер произв CAT25C256
Описание 128K/256K-Bit SPI Serial CMOS E2PROM
Производители Catalyst Semiconductor
логотип Catalyst Semiconductor логотип 

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CAT25C256 Даташит, Описание, Даташиты
CAT25C128/256
128K/256K-Bit SPI Serial CMOS E2PROM
FEATURES
s 5 MHz SPI Compatible
s 1.8 to 6.0 Volt Operation
s Hardware and Software Protection
s Zero Standby Current
s Low Power CMOS Technology
s SPI Modes (0,0 &1,1)
s Commercial, Industrial and Automotive
Temperature Ranges
DESCRIPTION
s 100,000 Program/Erase Cycles
s 100 Year Data Retention
s Self-Timed Write Cycle
s 8-Pin DIP/SOIC, 16-Pin SOIC, 14-Pin TSSOP
and 20-Pin TSSOP
s 64-Byte Page Write Buffer
s Block Write Protection
– Protect 1/4, 1/2 or all of E2PROM Array
The CAT25C128/256 is a 128K/256K-Bit SPI Serial
CMOS E2PROM internally organized as 16Kx8/32Kx8
bits. Catalyst’s advanced CMOS Technology substan-
tially reduces device power requirements. The
CAT25C128/256 features a 64-byte page write buffer.
The device operates via the SPI bus serial interface and
is enabled though a Chip Select (CS). In addition to the
Chip Select, the clock input (SCK), data in (SI) and data
out (SO) are required to access the device. The HOLD
pin may be used to suspend any serial communication
without resetting the serial sequence. The CAT25C128/
256 is designed with software and hardware write pro-
tection features including Block Lock protection. The
device is available in 8-pin DIP, 8-pin SOIC, 16-pin
SOIC, 14-pin TSSOP and 20-pin TSSOP packages.
PIN CONFIGURATION
SOIC Package (S, K) TSSOP Package (U14) DIP Package (P)
CS
SO
WP
VSS
1
2
3
4
8 VCC
7 HOLD
6 SCK
5 SI
SOIC Package (S16)
CS 1
SO 2
NC 3
NC 4
NC 5
WP 6
VSS 7
14 VCC
13 HOLD
12 NC
11 NC
10 NC
9 SCK
8 SI
CS
SO
WP
VSS
1
2
3
4
8 VCC
7 HOLD
6 SCK
5 SI
CS 1
SO 2
NC 3
NC 4
NC 5
NC 6
WP 7
VSS 8
16 VCC
15 HOLD
14 NC
13 NC
12 NC
11 NC
10 SCK
9 SI
PIN FUNCTIONS
TSSOP Package (U20)
NC 1
CS 2
SO 3
SO 4
NC 5
NC 6
WP 7
VSS 8
NC 9
NC 10
20 NC
19 VCC
18 HOLD
17 HOLD
16 NC
15 NC
14 SCK
13 SI
12 NC
11 NC
SO
SI
CS
WP
HOLD
SCK
Pin Name
SO
SCK
WP
VCC
VSS
CS
SI
HOLD
Function
Serial Data Output
Serial Clock
Write Protect
+1.8V to +6.0V Power Supply
Ground
Chip Select
Serial Data Input
Suspends Serial Input
BLOCK DIAGRAM
SENSE AMPS
SHIFT REGISTERS
WORD ADDRESS
BUFFERS
COLUMN
DECODERS
I/O
CONTROL
SPI
CONTROL
LOGIC
BLOCK
PROTECT
LOGIC
STATUS
REGISTER
XDEC
E2PROM
ARRAY
DATA IN
STORAGE
HIGH VOLTAGE/
TIMING CONTROL
25C128 F02
NC No Connect
Note: CAT25C256 not available in 8-Lead S or U packages.
© 2001 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 25088-00 1/01









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CAT25C256 Даташит, Описание, Даташиты
CAT25C128/256
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature ....................... –65°C to +150°C
Voltage on any Pin with
Respect to VSS(1) .................. –2.0V to +VCC +2.0V
VCC with Respect to VSS ................................ –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100 mA
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica-
tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
mance and reliability.
RELIABILITY CHARACTERISTICS
Symbol
NEND(3)
TDR(3)
VZAP(3)
ILTH(3)(4)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-Up
Min.
100,000
100
2000
100
Max.
Units
Cycles/Byte
Years
Volts
mA
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
D.C. OPERATING CHARACTERISTICS
VCC = +1.8V to +6.0V, unless otherwise specified.
Symbol
ICC1
ICC2
ISB
ILI
ILO
Parameter
Power Supply Current
(Operating Write)
Power Supply Current
(Operating Read)
Power Supply Current
(Standby)
Input Leakage Current
Output Leakage Current
Min.
Limits
Typ.
Max.
10
2
0
2
3
VIL(3)
VIH(3)
VOL1
VOH1
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
-1
VCC x 0.7
VCC - 0.8
VCC x 0.3
VCC + 0.5
0.4
Units
mA
mA
µA
µA
µA
V
V
V
V
Test Conditions
VCC = 5V @ 5MHz
SO=open; CS=Vss
VCC = 5.5V
FCLK = 5MHz
CS = VCC
VIN = VSS or VCC
VOUT = 0V to VCC,
CS = 0V
4.5VVCC<5.5V
IOL = 3.0mA
IOH = -1.6mA
VOL2
VOH2
Output Low Voltage
Output High Voltage
VCC-0.2
0.2 V 1.8VVCC<2.7V
V IOL = 150µA
IOH = -100µA
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.
Doc. No. 25088-00 1/01
2









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CAT25C256 Даташит, Описание, Даташиты
CAT25C128/256
Figure 1. Sychronous Data Timing
VIH
CS
SCK
VIL
tCSS
VIH
VIL
VIH
SI
VIL
tWH
tSU tH
VALID IN
VOH
SO
VOL
HI-Z
Note: Dashed Line= mode (1, 1) — — — —
A.C. CHARACTERISTICS (CAT25C128)
tCS
tCSH
tWL
tRI
tFI
tV
tHO
tDIS
HI-Z
SYMBOL PARAMETER
Vcc=
1.8V-6.0V
Min. Max.
Limits
VCC =
2.5V-6.0V
Min. Max.
VCC =
4.5V-5.5V
Min. Max.
tSU Data Setup Time
tH Data Hold Time
100 70
100 70
35
35
tWH
tWL
fSCK
tLZ
tRI(1)
tFI(1)
tHD
tCD
SCK High Time
SCK Low Time
Clock Frequency
HOLD to Output Low Z
Input Rise Time
Input Fall Time
HOLD Setup Time
HOLD Hold Time
250 150
250 150
DC 1 DC
50
2
2
250 250
250 250
80
80
3 DC 5
50 50
22
22
40
40
tWC Write Cycle Time
10 10
5
tV Output Valid from Clock Low
250 250
80
tHO Output Hold Time
00
0
tDIS Output Disable Time
250 250
100
tHZ HOLD to Output High Z
150 150
50
tCS CS High Time
1000
250
100
tCSS CS Setup Time
1000
250
100
tCSH CS Hold Time
1000
250
100
tWPS
WP Setup Time
50 50
50
tWPH
WP Hold Time
50 50
50
NOTE:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
3
UNITS
ns
ns
ns
ns
MHz
ns
µs
µs
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
Test
Conditions
CL = 50pF
Doc. No. 25088-00 1/01










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Catalyst Semiconductor

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