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CAT25C64 PDF даташит

Спецификация CAT25C64 изготовлена ​​​​«Catalyst Semiconductor» и имеет функцию, называемую «32K/64K-Bit SPI Serial CMOS E2PROM».

Детали детали

Номер произв CAT25C64
Описание 32K/64K-Bit SPI Serial CMOS E2PROM
Производители Catalyst Semiconductor
логотип Catalyst Semiconductor логотип 

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CAT25C64 Даташит, Описание, Даташиты
Advance Information
CAT25C64/128
64K/128K-Bit SPI Serial CMOS E2PROM
FEATURES
s 5 MHz SPI Compatible
s 1.8 to 6.0 Volt Operation
s Hardware and Software Protection
s Zero Standby Current
s Low Power CMOS Technology
s SPI Modes (0,0)
s Commercial, Industrial and Automotive
Temperature Ranges
DESCRIPTION
s 1,000,000 Program/Erase Cycles
s 100 Year Data Retention
s Self-Timed Write Cycle
s 8-Pin DIP/SOIC, 16-Pin SOIC and 20-Pin TSSOP
s 64-Byte Page Write Buffer
s Block Write Protection
– Protect 1/4, 1/2 or all of E2PROM Array
The CAT25C64/128 is a 64K/128K-Bit SPI Serial CMOS
E2PROM internally organized as 8Kx8/16Kx8 bits.
Catalyst’s advanced CMOS Technology substantially
reduces device power requirements. The CAT25C64/
128 features a 64-byte page write buffer. The device
operates via the SPI bus serial interface and is enabled
though a Chip Select (CS). In addition to the Chip Select,
the clock input (SCK), data in (SI) and data out (SO) are
required to access the device. The HOLD pin may be
used to suspend any serial communication without
resetting the serial sequence. The CAT25C64/128 is
designed with software and hardware write protection
features including Block write protection. The device is
available in 8-pin DIP, 8-pin SOIC, 16-pin SOIC and 20-
pin TSSOP packages.
PIN CONFIGURATION
BLOCK DIAGRAM
SOIC Package (S) SOIC Package (S16) TSSOP Package (U20)
CS
SO
WP
VSS
1
2
3
4
8
7
VCC
HOLD
CS
1
6 SCK
SO 2
5 SI
NC 3
NC 4
DIP Package (P)
NC 5
NC 6
CS 1
SO 2
8 VCC
7 HOLD
WP 7
VSS 8
WP
VSS
3
4
6 SCK
5 SI
16 VCC NC 1
15 HOLD CS 2
14
NC
SO 3
SO 4
13 NC NC 5
12 NC NC 6
WP 7
11 NC VSS 8
10 SCK NC 9
9 SI
NC 10
PIN FUNCTIONS
Pin Name
Function
SO
SCK
Serial Data Output
Serial Clock
20 NC
19 VCC
18 HOLD
17 HOLD
16 NC
15 NC
14 SCK
13 SI
12 NC
11 NC
WORD ADDRESS
BUFFERS
SENSE AMPS
SHIFT REGISTERS
COLUMN
DECODERS
SO
SI
CS
WP
HOLD
SCK
I/O
CONTROL
SPI
CONTROL
LOGIC
XDEC
E2PROM
ARRAY
WP Write Protect
VCC +1.8V to +6.0V Power Supply
BLOCK
PROTECT
LOGIC
VSS Ground
CS Chip Select
DATA IN
STORAGE
SI
HOLD
NC
Serial Data Input
Suspends Serial Input
No Connect
STATUS
REGISTER
HIGH VOLTAGE/
TIMING CONTROL
25C128 F02
© 1999 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc No. 25069-00 6/99 SPI-1









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CAT25C64 Даташит, Описание, Даташиты
CAT25C64/128
Advance Information
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature ....................... –65°C to +150°C
Voltage on any Pin with
Respect to Ground(1) ............ –2.0V to +VCC +2.0V
VCC with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100 mA
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica-
tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
mance and reliability.
RELIABILITY CHARACTERISTICS
Symbol
NEND(3)
TDR(3)
VZAP(3)
ILTH(3)(4)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-Up
Min.
1,000,000
100
2000
100
Max.
Units
Cycles/Byte
Years
Volts
mA
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
D.C. OPERATING CHARACTERISTICS
VCC = +1.8V to +6.0V, unless otherwise specified.
Symbol
ICC1
ICC2
ISB
ILI
ILO
Parameter
Power Supply Current
(Operating Write)
Power Supply Current
(Operating Read)
Power Supply Current
(Standby)
Input Leakage Current
Output Leakage Current
Min.
Limits
Typ.
Max.
10
2
0
2
3
VIL(3)
VIH(3)
VOL1
VOH1
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
-1
VCC x 0.7
VCC - 0.8
VCC x 0.3
VCC + 0.5
0.4
Units
mA
mA
µA
µA
µA
V
V
V
V
Test Conditions
VCC = 5V @ 5MHz
SO=open; CS=Vss
VCC = 5.5V
FCLK = 5MHz
CS = VCC
VIN = VSS or VCC
VOUT = 0V to VCC,
CS = 0V
4.5VVCC<5.5V
IOL = 3.0mA
IOH = -1.6mA
VOL2
VOH2
Output Low Voltage
Output High Voltage
VCC-0.2
0.2 V 1.8VVCC<2.7V
V IOL = 150µA
IOH = -100µA
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.
Doc. No. 25069-00 6/99 SPI-1
2









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CAT25C64 Даташит, Описание, Даташиты
Advance Information
CAT25C64/128
Figure 1. Sychronous Data Timing
VIH
CS
SCK
SI
VIL
tCSS
VIH
VIL
VIH
VIL
tWH
tSU tH
VALID IN
VOH
SO
VOL
HI-Z
tCS
tCSH
tWL
tRI
tFI
tV
tHO
tDIS
HI-Z
A.C. CHARACTERISTICS
SYMBOL PARAMETER
Vcc=
1.8V-6V
Min. Max.
Limits
VCC =
2.5V-6V
Min. Max.
VCC =
4.5V-5.5V
Min. Max.
Test
UNITS Conditions
tSU Data Setup Time
100 70
35
ns
tH Data Hold Time
100 70
35
ns
tWH SCK High Time
250 150
80
ns
tWL SCK Low Time
250 150
80
ns
fSCK
tLZ
tRI(1)
tFI(1)
tHD
tCD
Clock Frequency
HOLD to Output Low Z
Input Rise Time
Input Fall Time
HOLD Setup Time
HOLD Hold Time
DC 1 DC
50
2
2
250 250
250 250
3 DC 5
50 50
22
22
40
40
MHz
ns
µs
µs
ns
ns
CL = 50pF
tWC Write Cycle Time
10 10
5 ms
tV Output Valid from Clock Low
250
220
100 ns
tHO Output Hold Time
00
0
ns
tDIS Output Disable Time
250 250
100 ns
tHZ HOLD to Output High Z
150 150
50 ns
tCS CS High Time
1000
330
200
ns
tCSS CS Setup Time
1000
100
100
ns
tCSH
CS Hold Time
1000
100
100
ns
NOTE:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
3 Doc No. 25069-00 6/99 SPI-1










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