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PDF CAT28HT64 Data sheet ( Hoja de datos )
| Número de pieza | CAT28HT64 | |
| Descripción | 64K-Bit CMOS PARALLEL E2PROM | |
| Fabricantes | Catalyst Semiconductor | |
| Logotipo |  |
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CAT28HT64
64K-Bit CMOS PARALLEL E2PROM
FEATURES
s Fast Read Access Times:
– 150/200ns
s Low Power CMOS Dissipation:
– Active: 25 mA Max.
– Standby: 300 µA Max.
s Simple Write Operation:
– On-Chip Address and Data Latches
– Self-Timed Write Cycle with Auto-Clear
s Fast Write Cycle Time:
– 5ms Max.
s CMOS and TTL Compatible I/O
Extended Temperature: 170˚C
s Hardware and Software Write Protection
s Automatic Page Write Operation:
– 1 to 32 Bytes in 5ms
– Page Load Timer
s End of Write Detection:
– Toggle Bit
– DATA Polling
s 100,000 Program/Erase Cycles
s 100 Year Data Retention
DESCRIPTION
The CAT28HT64 is a fast, low power, 5V-only CMOS
parallel E2PROM organized as 8K x 8-bits. It requires a
simple interface for in-system programming. On-chip
address and data latches, self-timed write cycle with
auto-clear and VCC power up/down write protection
eliminate additional timing and protection hardware.
DATA Polling and Toggle status bits signal the start and
end of the self-timed write cycle. Additionally, the
CAT28HT64 features hardware and software write pro-
tection.
The CAT28HT64 is manufactured using Catalyst’s ad-
vanced CMOS floating gate technology. It is designed to
endure 100,000 program/erase cycles and has a data
retention of 100 years. The device is available in JEDEC-
approved 28-pin Ceramic DIP package.
BLOCK DIAGRAM
A5–A12
ADDR. BUFFER
& LATCHES
VCC
CE
OE
WE
INADVERTENT
WRITE
PROTECTION
CONTROL
LOGIC
A0–A4
TIMER
ADDR. BUFFER
& LATCHES
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
ROW
DECODER
HIGH VOLTAGE
GENERATOR
DATA POLLING
AND
TOGGLE BIT
COLUMN
DECODER
8-39
8,192 x 8
E2PROM
ARRAY
32 BYTE PAGE
REGISTER
I/O BUFFERS
I/O0–I/O7
5094 FHD F02
1 page  
Advanced
CAT28HT64
A.C. CHARACTERISTICS, Write Cycle
VCC = 5V ±10%, unless otherwise specified. (Temperature 0˚C to 170˚C)
Symbol
tWC
tAS
tAH
tCS
tCH
tCW(2)
tOES
tOEH
tWP(2)
tDS
tDH
tINIT(1)
tBLC(1)(3)
Parameter
Write Cycle Time
Address Setup Time
Address Hold Time
CE Setup Time
CE Hold Time
CE Pulse Time
OE Setup Time
OE Hold Time
WE Pulse Width
Data Setup Time
Data Hold Time
Write Inhibit Period After Power-up
Byte Load Cycle Time
28HT64-12
Min. Max.
5
0
100
0
0
110
0
0
110
60
0
5 10
.05 100
28HT64-15
Min. Max.
5
0
100
0
0
110
0
0
110
60
0
5 10
.05 100
28HT64-20
Min. Max.
5
0
100
0
0
110
0
0
110
60
0
5 10
.05 100
Units
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
µs
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) A write pulse of less than 20ns duration will not initiate a write cycle.
(3) A timer of duration tBLC max. begins with every LOW to HIGH transition of WE. If allowed to time out, a page or byte write will begin;
however a transition from HIGH to LOW within tBLC max. stops the timer.
8-43
Stock No. 21064-04 2/98
5 Page | ||
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| PDF Descargar | [ Datasheet CAT28HT64.PDF ] | |
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