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CAT28LV256 PDF даташит

Спецификация CAT28LV256 изготовлена ​​​​«Catalyst Semiconductor» и имеет функцию, называемую «256K-Bit CMOS PARALLEL E2PROM».

Детали детали

Номер произв CAT28LV256
Описание 256K-Bit CMOS PARALLEL E2PROM
Производители Catalyst Semiconductor
логотип Catalyst Semiconductor логотип 

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CAT28LV256 Даташит, Описание, Даташиты
CAT28LV256
256K-Bit CMOS PARALLEL E2PROM
FEATURES
s 3.0V to 3.6V Supply
s Read Access Times: 200/250/300 ns
s Low Power CMOS Dissipation:
– Active: 15 mA Max.
– Standby: 150 µA Max.
s Simple Write Operation:
– On-Chip Address and Data Latches
– Self-Timed Write Cycle with Auto-Clear
s Fast Write Cycle Time:
– 10ms Max.
s Commercial, Industrial and Automotive
Temperature Ranges
s CMOS and TTL Compatible I/O
s Automatic Page Write Operation:
– 1 to 64 Bytes in 10ms
– Page Load Timer
s End of Write Detection:
– Toggle Bit
DATA Polling
s Hardware and Software Write Protection
s 100,000 Program/Erase Cycles
s 100 Year Data Retention
DESCRIPTION
The CAT28LV256 is a fast, low power, low voltage
CMOS Parallel E2PROM organized as 32K x 8-bits. It
requires a simple interface for in-system programming.
On-chip address and data latches, self-timed write cycle
with auto-clear and VCC power up/down write protection
eliminate additional timing and protection hardware.
DATA Polling and Toggle status bits signal the start and
end of the self-timed write cycle. Additionally, the
CAT28LV256 features hardware and software write
protection.
BLOCK DIAGRAM
The CAT28LV256 is manufactured using Catalyst’s
advanced CMOS floating gate technology. It is designed
to endure 100,000 program/erase cycles and has a data
retention of 100 years. The device is available in JEDEC–
approved 28-pin DIP, 28-pin TSOP or 32-pin PLCC
packages.
A6–A14
VCC
CE
OE
WE
A0–A5
ADDR. BUFFER
& LATCHES
INADVERTENT
WRITE
PROTECTION
CONTROL
LOGIC
TIMER
ADDR. BUFFER
& LATCHES
ROW
DECODER
HIGH VOLTAGE
GENERATOR
DATA POLLING
AND
TOGGLE BIT
COLUMN
DECODER
32,768 x 8
E2PROM
ARRAY
64 BYTE PAGE
REGISTER
I/O BUFFERS
I/O0–I/O7
28LV256 F01
© 2001 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 25040-00 4/01 P-1









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CAT28LV256 Даташит, Описание, Даташиты
CAT28LV256
PIN CONFIGURATION
DIP Package (P)
PLCC Package (N)
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
1 28
2 27
3 26
4 25
5 24
6 23
7 22
8 21
9 20
10 19
11 18
12 17
13 16
14 15
VCC
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
4 3 2 1 32 31 30
A6 5
29 A8
A5 6
28 A9
A4 7
27 A11
A3 8
26 NC
A2 9
TOP VIEW
25 OE
A1 10
24 A10
A0 11
23 CE
NC 12
22 I/O7
I/O0 13
21 I/O6
14 15 16 17 18 19 20
28LV256 F02
TSOP Top View (8mm X 13.4mm) (T13)
OE
A11
A9
A8
A13
WE
VCC
A14
A12
A7
A6
A5
A4
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 A10
27 CE
26 I/O7
25 I/O6
24 I/O5
23 I/O4
22 I/O3
21 GND
20 I/O2
19 I/O1
18 I/O0
17 A0
16 A1
15 A2
28LV256 F03
PIN FUNCTIONS
Pin Name
Function
A0–A14
Address Inputs
I/O0–I/O7
CE
Data Inputs/Outputs
Chip Enable
OE Output Enable
Pin Name
WE
VCC
VSS
NC
Function
Write Enable
3.0 to 3.6 V Supply
Ground
No Connect
Doc. No. 25040-00 4/01 P-1
2









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CAT28LV256 Даташит, Описание, Даташиты
CAT28LV256
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature ....................... –65°C to +150°C
Voltage on Any Pin with
Respect to Ground(2) ........... –2.0V to +VCC + 2.0V
VCC with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(3) ........................ 100 mA
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica-
tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
mance and reliability.
RELIABILITY CHARACTERISTICS
Symbol
NEND(1)
TDR(1)
VZAP(1)
ILTH(1)(4)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-Up
Min.
100,000
100
2000
100
Max.
Units
Cycles/Byte
Years
Volts
mA
Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
CAPACITANCE TA = 25°C, f = 1.0 MHz
Symbol
Test
CI/O(1)
Input/Output Capacitance
CIN(1)
Input Capacitance
Max.
10
6
Units
pF
pF
Conditions
VI/O = 0V
VIN = 0V
MODE SELECTION
Mode
CE WE OE I/O Power
Read
L
H
L
DOUT
ACTIVE
Byte Write (WE Controlled)
L
H DIN ACTIVE
Byte Write (CE Controlled)
L H DIN ACTIVE
Standby, and Write Inhibit
H
X
X
High-Z
STANDBY
Read and Write Inhibit
X
H
H
High-Z
ACTIVE
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.
(3) Output shorted for no more than one second. No more than one output shorted at a time.
(4) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC +1V.
3 Doc. No. 25040-00 4/01 P-1










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Номер в каталогеОписаниеПроизводители
CAT28LV256256K-Bit CMOS PARALLEL E2PROMCatalyst Semiconductor
Catalyst Semiconductor

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