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CAT34RC02PITE13REV-E PDF даташит

Спецификация CAT34RC02PITE13REV-E изготовлена ​​​​«Catalyst Semiconductor» и имеет функцию, называемую «2-kb I2C Serial EEPROM/ Serial Presence Detect».

Детали детали

Номер произв CAT34RC02PITE13REV-E
Описание 2-kb I2C Serial EEPROM/ Serial Presence Detect
Производители Catalyst Semiconductor
логотип Catalyst Semiconductor логотип 

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CAT34RC02PITE13REV-E Даташит, Описание, Даташиты
CAT34RC02
2-kb I2C Serial EEPROM, Serial Presence Detect
FEATURES
ALOGEN FR
LEAD
F
R
E
E
TM
I 400 kHz I2C bus compatible*
I 1.7 to 5.5 volt operation
I 16-byte page write buffer
I Hardware write protection for entire memory
I Permanent and reversible software write
protection for lower 128 bytes
I Schmitt trigger on SCL and SDA inputs
I Low power CMOS technology
I 1,000,000 program/erase cycles
I 100 year data retention
I 8-pin DIP, SOIC, TSSOP and TDFN packages
I Industrial and extended temperature ranges
DESCRIPTION
The CAT34RC02 is a 2-kb Serial CMOS EEPROM
internally organized as 256 words of 8 bits each. Catalyst’s
advanced CMOS technology substantially reduces
device power requirements. The CAT34RC02 features
a 16-byte page write buffer. The device operates via the
I2C bus serial interface and is available in 8-pin DIP,
SOIC, TSSOP and TDFN packages.
PIN CONFIGURATION
DIP Package (P, L)
A0
A1
A2
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
SOIC Package (J, W)
A0
A1
A2
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
FUNCTIONAL SYMBOL
VCC
SCL
TDFN Package (SP2, VP2)
A0 1
A1 2
A2 3
VSS 4
8 VCC
7 WP
6 SCL
5 SDA
A2, A1, A0
WP
CAT34RC02
VSS
SDA
TSSOP Package (U, Y)
A0
A1
A2
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
PIN FUNCTIONS
Pin Name
Function
A0, A1, A2 Device Address Inputs
SDA
Serial Data/Address
SCL Serial Clock
WP Write Protect
VCC 1.7 V to 5.5 V Power Supply
VSS Ground
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc No. 1052, Rev. K









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CAT34RC02PITE13REV-E Даташит, Описание, Даташиты
CAT34RC02
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias .................. -55°C to +125°C
Storage Temperature ........................ -65°C to +150°C
Voltage on Any Pin with
Respect to Ground(1) ............ -2.0 V to VCC + 2.0 V
Voltage on A0 .................................................. -2.0 V to +12.0 V
VCC with Respect to VSS .............................. -2.0 V to +7.0 V
*COMMENT
Stresses above those listed under Absolute Maximum Ratingsmay
cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions
outside of those listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for extended periods
may affect device performance and reliability.
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Reference Test Method
NEND(2)(*)
Endurance
TDR(2)(*) Data Retention
VZAP(2)(*) ESD Susceptibility
ILTH(2)(3)
Latch-up
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
(*) Page Mode, VCC = 5 V, 25°C
D.C. OPERATING CHARACTERISTICS
VCC = 1.7 V to 5.5 V, unless otherwise specified.
Min
1,000,000
100
4000
100
Units
Program/ Erase Cycles
Years
Volts
mA
Symbol
Parameter
Test Conditions
Min
Typ
Max Units
ICC
Power Supply Current (Read)
fSCL = 100 kHz
1 mA
ICC
ISB(4)
Power Supply Current (Write)
Standby Current (VCC = 5.0 V)
fSCL = 100 kHz
VIN = GND or VCC
3 mA
1 µA
ILI
Input Leakage Current
VIN = GND to VCC
1 µA
ILO
Output Leakage Current
VOUT = GND to VCC
1 µA
VIL Input Low Voltage
1
VCC x 0.3
V
VIH Input High Voltage
VCC x 0.7
VCC + 1.0 V
VOL1 Output Low Voltage (VCC = 3.0 V)
IOL = 3 mA
0.4 V
VOL2 Output Low Voltage (VCC = 1.7 V) IOL = 1.5 mA
0.5 V
VHV
RSWP Set/Clear Overdrive
VHV - VCC > 4.8 V
A0 High Voltage
7
10 V
CAPACITANCE TA = 25°C, f = 400 kHz, VCC = 5 V
Symbol
Test
Conditions
Min Typ
Max Units
CI/O(2)
CIN(2)
Input/Output Capacitance (SDA)
Input Capacitance (other pins)
VI/O = 0 V
VIN = 0 V
8 pF
6 pF
ZWPL
WP Input Impedance
VIN < 0.5 V
5
70 k
ZWPH
WP Input Impedance
VIN > VCC x 0.7
500
k
Note:
(1) The DC input voltage on any pin should not be lower than -0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin
may undershoot to no less than -2.0 V or overshoot to no more than VCC + 2.0 V, for periods of less than 20 ns. The maximum DC
voltage on address pin A0 is +12.0 V.
(2) This parameter is tested initially and after a design or process change that affects the parameter.
(3) Latch-up protection is provided for stresses up to 100 mA on I/O pins from -1.0 V to VCC + 1.0 V.
(4) Standby Current, ISB = 10 µA max at extended temperature range.
Doc. No. 1052, Rev. K
2









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CAT34RC02PITE13REV-E Даташит, Описание, Даташиты
CAT34RC02
A.C. CHARACTERISTICS
VCC = 1.7 V to 5.5 V, unless otherwise specified.
Read & Write Cycle Limits
Symbol
Parameter
FSCL
TI(1)
tAA
tBUF(1)
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR(1)
tF(1)
tSU:STO
tDH
Clock Frequency
Noise Suppression Time
Constant at SCL, SDA Inputs
SCL Low to SDA Data Out
and ACK Out
Time the Bus Must be Free Before
a New Transmission Can Start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time
(for a Repeated Start Condition)
Data In Hold Time
Data In Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
1.7 V - 5.5 V
Min Max
100
100
3.5
4.7
4
4.7
4
4.7
0
250
1
300
4
100
2.5 V - 5.5 V
Min Max
400
100
0.9
1.3
0.6
1.3
0.6
0.6
0
100
0.3
300
0.6
100
Units
kHz
ns
µs
µs
µs
µs
µs
µs
ns
ns
µs
ns
µs
ns
Power-Up Timing(1)(2)
Symbol
Parameter
tPUR
tPUW
Power-up to Read Operation
Power-up to Write Operation
Min Typ
Max
1
1
Units
ms
ms
Write Cycle Limits
Symbol
Parameter
tWR Write Cycle Time
Min Typ
Max
5
Units
ms
The write cycle time is the time elapsed between the
STOP command (following the write instruction) and the
completion of the internal write cycle. During the internal
write cycle, SDA is released by the Slave and the device
does not acknowledge external commands.
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
3 Doc No. 1052, Rev. K










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Catalyst Semiconductor

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