CAT34WC02 Datasheet PDF - Catalyst Semiconductor
| Part Number | CAT34WC02 | |
| Description | 2K-Bit I2C Serial EEPROM/ Serial Presence Detect | |
| Manufacturers | Catalyst Semiconductor | |
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CAT34WC02
2K-Bit I2C Serial EEPROM, Serial Presence Detect
FEATURES
s 400 KHz (5V) and 100 KHz (1.8V) I2C bus
compatible
s 1.8 to 6.0 volt operation
s Low power CMOS technology
– zero standby current
s 16-byte page write buffer
s Commercial, industrial and automotive
temperature ranges
DESCRIPTION
The CAT34WC02 is a 2K-bit Serial CMOS EEPROM
internally organized as 256 words of 8 bits each. Catalyst’s
advanced CMOS technology substantially reduces de-
vice power requirements. The CAT34WC02 features a
s Self-timed write cycle with auto-clear
s Software write protection for lower 128 bytes
s 1,000,000 program/erase cycles
s 100 year data retention
s 8-pin DIP, 8-pin SOIC and 8-pin TSSOP packages
s 256 x 8 memory organization
s Hardware write protect
16-byte page write buffer. The device operates via the
I2C bus serial interface and is available in 8-pin DIP, 8-
pin SOIC or 8-pin TSSOP packages.
PIN CONFIGURATION
DIP Package (P)
SOIC Package (J)
A0
A1
A2
VSS
1
2
3
4
8 VCC
A0
7 WP
A1
6 SCL
A2
5 SDA VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
TSSOP Package (U)
A0
A1
A2
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
BLOCK DIAGRAM
EXTERNAL LOAD
VCC
VSS
DOUT
ACK
WORD ADDRESS
BUFFERS
SDA
START/STOP
LOGIC
SENSE AMPS
SHIFT REGISTERS
COLUMN
DECODERS
XDEC
E2PROM
WP CONTROL
LOGIC
PIN FUNCTIONS
Pin Name
Function
A0, A1, A2 Device Address Inputs
SDA
Serial Data/Address
SCL Serial Clock
WP Write Protect
VCC +1.8V to +6.0V Power Supply
VSS Ground
SCL
A0
A1
A2
STATE COUNTERS
SLAVE
ADDRESS
COMPARATORS
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
DATA IN STORAGE
HIGH VOLTAGE/
TIMING CONTROL
24CXX F03
© 2001 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc No. 1003, Rev. A
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CAT34WC02
I2C BUS PROTOCOL
The following defines the features of the I2C bus proto-
col:
(1) Data transfer may be initiated only when the bus is
not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT34WC02 monitor the
SDA and SCL lines and will not respond until this
condition is met.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
DEVICE ADDRESSING
The Master begins a transmission by sending a START
condition. The Master then sends the address of the
particular slave device it is requesting. The four most
significant bits of the 8-bit slave address are fixed
(except when accessing the Write Protect Register) as
1010 for the CAT34WC02 (see Fig. 5). The next three
significant bits (A2, A1, A0) are the device address bits
and define which device the Master is accessing. Up to
eight CAT34WC02 may be individually addressed by
the system. The last bit of the slave address specifies
whether a Read or Write operation is to be performed.
When this bit is set to 1, a Read operation is selected,
and when set to 0, a Write operation is selected.
After the Master sends a START condition and the slave
address byte, the CAT34WC02 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT34WC02 then performs a Read or a Write operation
depending on the state of the R/W bit.
Acknowledge
After a successful data transfer, each receiving device is
required to generate an acknowledge. The Acknowledg-
ing device pulls down the SDA line during the ninth clock
cycle, signaling that it received the 8 bits of data.
The CAT34WC02 responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation,
it responds with an acknowledge after receiving each
byte.
When the CAT34WC02 begins a READ mode, it trans-
mits 8 bits of data, releases the SDA line, and monitors
the line for an acknowledge. Once it receives this ac-
knowledge, the CAT34WC02 will continue to transmit
data. If no acknowledge is sent by the Master, the device
terminates data transmission and waits for a STOP
condition.
Figure 4. Acknowledge Timing
SCL FROM
MASTER
1
89
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
Figure 5. Slave Address Bits
1 0 1 0 A2 A1 A0 R/W Normal Read and Write
DEVICE ADDRESS
0
1
1
0
A2
A1
A0
R/W
Programming the Write
Protect Register
5020 FHD F06
34WC02 F07
5 Doc No. 1003, Rev. A
Preview 5 Page |
Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for CAT34WC02 electronic component. |
| Information | Total 10 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ CAT34WC02.PDF Datasheet ] | |
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