C8051F506 Datasheet PDF - Silicon Laboratories
| Part Number | C8051F506 | |
| Description | Mixed Signal ISP Flash MCU | |
| Manufacturers | Silicon Laboratories | |
| Logo |  |
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Analog Peripherals
- 12-Bit ADC
• Up to 200 ksps
• Up to 32 external single-ended inputs
• VREF from on-chip VREF, external pin or VDD
• Internal or external start of conversion source
• Built-in temperature sensor
- Two Comparators
• Programmable hysteresis and response time
• Configurable as interrupt or reset source
• Low current
On-Chip Debug
- On-chip debug circuitry facilitates full speed, non-
intrusive in-system debug (no emulator required)
- Provides breakpoints, single stepping,
inspect/modify memory and registers
- Superior performance to emulation systems using
ICE-chips, target pods, and sockets
- Low cost, complete development kit
Supply Voltage 1.8 to 5.25 V
- Typical operating current: 19 mA at 50 MHz;
- Typical stop mode current: 2 µA
High-Speed 8051 µC Core
- Pipelined instruction architecture; executes 70% of
instructions in 1 or 2 system clocks
- Up to 50 MIPS throughput with 50 MHz clock
- Expanded interrupt handler
C8051F50x/F51x
Mixed Signal ISP Flash MCU Family
Memory
- 4352 bytes internal data RAM (256 + 4096 XRAM)
- 64 or 32 kB Flash; In-system programmable in
512-byte Sectors
Digital Peripherals
- 40, 33, or 25 Port I/O; All 5 V tolerant
- CAN 2.0 Controller—no crystal required
- LIN 2.1 Controller (Master and Slave capable); no
crystal required
- Hardware enhanced UART, SMBus™, and
enhanced SPI™ serial ports
- Four general purpose 16-bit counter/timers
- 16-Bit programmable counter array (PCA) with six
capture/compare modules and enhanced PWM
functionality
Clock Sources
- Internal 24 MHz with ±0.5% accuracy for CAN and
master LIN operation
- External oscillator: Crystal, RC, C, or clock
(1 or 2 pin modes)
- Can switch between clock sources on-the-fly;
useful in power saving modes
Packages
- 48-Pin QFP/QFN (C8051F500/1/4/5)
- 40-Pin QFN (C8051F508/9-F510/1)
- 32-Pin QFP/QFN (C8051F502/3/6/7)
Automotive Qualified
- Temperature Range: –40 to +125 °C
- Compliant to AEC-Q100
ANALOG
PERIPHERALS
A 12-bit
M
U
200 ksps
X ADC
TEMP
SENSOR
Voltage VREG
Comparators 0-1 VREF
DIGITAL I/O
UART 0
SMBus
SPI
PCA
Timers 0-3
CAN
LIN
Ports 0-4
Crossbar
External
Memory
Interface
24 MHz PRECISION
INTERNAL OSCILLATOR
2x Clock Multiplier
HIGH-SPEED CONTROLLER CORE
64 kB
ISP FLASH
FLEXIBLE
INTERRUPTS
8051 CPU
(50 MIPS)
DEBUG
CIRCUITRY
4 kB XRAM
POR WDT
Rev. 1.2 3/11
Copyright © 2011 by Silicon Laboratories C8051F500/1/2/3/4/5/6/7/8/9-F510/1
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C8051F50x/F51x
18.5. Memory Mode Selection................................................................................ 155
18.5.1. Internal XRAM Only .............................................................................. 155
18.5.2. Split Mode without Bank Select............................................................. 155
18.5.3. Split Mode with Bank Select.................................................................. 156
18.5.4. External Only......................................................................................... 156
18.6. Timing .......................................................................................................... 156
18.6.1. Non-Multiplexed Mode .......................................................................... 158
18.6.1.1. 16-bit MOVX: EMI0CF[4:2] = 101, 110, or 111............................. 158
18.6.1.2. 8-bit MOVX without Bank Select: EMI0CF[4:2] = 101 or 111 ....... 159
18.6.1.3. 8-bit MOVX with Bank Select: EMI0CF[4:2] = 110 ....................... 160
18.6.2. Multiplexed Mode .................................................................................. 161
18.6.2.1. 16-bit MOVX: EMI0CF[4:2] = 001, 010, or 011............................. 161
18.6.2.2. 8-bit MOVX without Bank Select: EMI0CF[4:2] = 001 or 011 ....... 162
18.6.2.3. 8-bit MOVX with Bank Select: EMI0CF[4:2] = 010 ....................... 163
19. Oscillators and Clock Selection ......................................................................... 165
19.1. System Clock Selection................................................................................. 165
19.2. Programmable Internal Oscillator .................................................................. 167
19.2.1. Internal Oscillator Suspend Mode ......................................................... 167
19.3. Clock Multiplier .............................................................................................. 170
19.4. External Oscillator Drive Circuit..................................................................... 172
19.4.1. External Crystal Example...................................................................... 174
19.4.2. External RC Example............................................................................ 175
19.4.3. External Capacitor Example.................................................................. 175
20. Port Input/Output ................................................................................................. 177
20.1. Port I/O Modes of Operation.......................................................................... 178
20.1.1. Port Pins Configured for Analog I/O...................................................... 178
20.1.2. Port Pins Configured For Digital I/O...................................................... 178
20.1.3. Interfacing Port I/O in a Multi-Voltage System ...................................... 179
20.2. Assigning Port I/O Pins to Analog and Digital Functions............................... 179
20.2.1. Assigning Port I/O Pins to Analog Functions ........................................ 179
20.2.2. Assigning Port I/O Pins to Digital Functions.......................................... 179
20.2.3. Assigning Port I/O Pins to External Digital Event Capture Functions ... 180
20.3. Priority Crossbar Decoder ............................................................................. 180
20.4. Port I/O Initialization ...................................................................................... 182
20.5. Port Match ..................................................................................................... 187
20.6. Special Function Registers for Accessing and Configuring Port I/O ............. 191
21. Local Interconnect Network (LIN)....................................................................... 201
21.1. Software Interface with the LIN Controller..................................................... 202
21.2. LIN Interface Setup and Operation................................................................ 202
21.2.1. Mode Definition ..................................................................................... 202
21.2.2. Baud Rate Options: Manual or Autobaud ............................................. 202
21.2.3. Baud Rate Calculations: Manual Mode................................................. 202
21.2.4. Baud Rate Calculations—Automatic Mode ........................................... 204
21.3. LIN Master Mode Operation .......................................................................... 205
21.4. LIN Slave Mode Operation ............................................................................ 206
Rev. 1.2
5
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