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PDF C1602A-YFDN-DYNC Data sheet ( Hoja de datos )
| Número de pieza | C1602A-YFDN-DYNC | |
| Descripción | LCD Module | |
| Fabricantes | KE FEI YAN | |
| Logotipo |  |
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C1602A-YFDN-DYNC
SPECIFICATION FOR
APPROVAL
Product Type: Character Type STN Dot Matrix
LCD Module
Part No.: C1602A-YFDN-DYNC
Customer:
Customer Part No.:
Date:
APPOVED SIGNATURES
BLUE MOON
Customer
KE FEI YAN DISPLAY CO.,LTD
1
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3. OUTLINE DEMENSION:
C1602A-YFDN-DYNC
4. BLOCK DIAGRAM:
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When N=High,2-line display mode is set.
F: Display font type control bit
When F=Low, 5X8 dots format display mode is set .
When F=High, 5X11 dots format display mode.
C1602A-YFDN-DYNC
Set CGRAM Address
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 1 AC5 AC4 AC3 AC2 AC1 AC0
Set CGRAM address to AC. This instruction makes CGRAM data available from MPU.
Set DDRAM Address
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 1 AC6 AC5 AC4 AC3 AC2 AC1 AC0
Set DDRAM address to AC. This instruction makes DDRAM data available from MPU. When 1-line
display mode (N=Low ),DDRAM address is from “00H” to “4FH”In 2-line display mode(N=High),
DDRAM address in the1st line is from “00H” to “27H” and DDRAM address in the 2nd line is from
“40H” to “67H”.
Read Busy Flag & Address
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 1 BF AC6 AC5 AC4 AC3 AC2 AC1 AC0
This instruction shows whether IC is in internal operation or not. If BF is high internal operation is in
progress and should wait until BF is to be Low, which by then the next instruction can be performed. In
this instruction you can also read the value lf the address counter.
Write data to RAM
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1 0 D7 D6 D5 D4 D3 D2 D1 D0
Write binary 8-bit data to DDRAM/CGRAM. The selection of RAM from DDRAM, and CGRAM, is
set by the previous address set instruction(DDRAM address set, CGRAM address set). RAM set
instruction can also determine the AC direction to RAM. After write operation, the address is
automatically increased/decreased by 1, according the entry mode.
Read data from RAM
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
1 1 D7 D6 D5 D4 D3 D2 D1 D0
Read binary 8-bit data from DDRAM/CGRAM. The selection of RAM is set by the previous address
set instruction. If the address set instruction of RAM is not performed before this instruction, the data
that has been read first is invalid, as the direction of AC is not yet determined. If RAM data is read
several times without RAM address instructions set before read operation, the correct RAM data can be
obtained from the second. But the first data would be incorrect, as there is no time margin to transfer
RAM data. In case of DDRAM read operation, cursor shift instruction plays the same role as DDRAM
address set instruction, it also transfers RAM data to output data register. After read operation, address
counter is automatically increased/decreased by 1 according to the entry mode.
After CGRAM read operation, display shift may not be executed correctly.
Note:
In case of RAM write operation, AC is increased/decreased by 1 as in read operation. At this time, AC
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