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CAT93C56 PDF даташит

Спецификация CAT93C56 изготовлена ​​​​«Catalyst Semiconductor» и имеет функцию, называемую «1K/2K/2K/4K/16K-Bit Microwire Serial E2PROM».

Детали детали

Номер произв CAT93C56
Описание 1K/2K/2K/4K/16K-Bit Microwire Serial E2PROM
Производители Catalyst Semiconductor
логотип Catalyst Semiconductor логотип 

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CAT93C56 Даташит, Описание, Даташиты
CAT93C46/56/57/66/86
1K/2K/2K/4K/16K-Bit Microwire Serial E2PROM
FEATURES
s High Speed Operation:
– 93C46/56/57/66: 1MHz
– 93C86: 3MHz
s Low Power CMOS Technology
s 1.8 to 6.0 Volt Operation
s Selectable x8 or x16 Memory Organization
s Self-Timed Write Cycle with Auto-Clear
s Hardware and Software Write Protection
s Power-Up Inadvertant Write Protection
s 1,000,000 Program/Erase Cycles
s 100 Year Data Retention
s Commercial, Industrial and Automotive
Temperature Ranges
s Sequential Read (except 93C46)
s Program Enable (PE) Pin (93C86 only)
DESCRIPTION
The CAT93C46/56/57/66/86 are 1K/2K/2K/4K/16K-bit
Serial E2PROM memory devices which are configured
as either registers of 16 bits (ORG pin at VCC) or 8 bits
(ORG pin at GND). Each register can be written (or read)
serially by using the DI (or DO) pin. The CAT93C46/56/
57/66/86 are manufactured using Catalyst’s advanced
CMOS E2PROM floating gate technology. The devices
are designed to endure 1,000,000 program/erase cycles
and have a data retention of 100 years. The devices are
available in 8-pin DIP, 8-pin SOIC or 8-pin TSSOP
packages.
PIN CONFIGURATION
DIP Package (P)
SOIC Package (J)
CS 1
SK 2
DI 3
DO 4
8 VCC
NC (PE*) 1
7 NC (PE*)
VCC
2
6 ORG
CS 3
5 GND
SK 4
8 ORG
7 GND
6 DO
5 DI
SOIC Package (S) SOIC Package (K)
CS 1
SK 2
DI 3
DO 4
8 VCC
CS 1
7 NC (PE*) SK 2
6 ORG
DI 3
5 GND
DO 4
8 VCC
7 NC (PE*)
6 ORG
5 GND
TSSOP Package (U)
CS 1
SK 2
DI 3
DO 4
8
7
6
5
VCC
NC (PE*)
ORG
GND
*Only For 93C86
PIN FUNCTIONS
Pin Name
Function
CS Chip Select
SK Clock Input
DI Serial Data Input
DO Serial Data Output
VCC
GND
+1.8 to 6.0V Power Supply
Ground
ORG
Memory Organization
NC No Connection
PE* Program Enable
Note: When the ORG pin is connected to VCC, the X16 organiza
tion is selected. When it is connected to ground, the X8 pin
is selected. If the ORG pin is left unconnected, then an
internal pullup device will select the X16 organization.
BLOCK DIAGRAM
VCC
GND
ORG
MEMORY ARRAY
ORGANIZATION
DATA
REGISTER
DI
MODE DECODE
CS LOGIC
PE*
CLOCK
SK GENERATOR
93C46/56/57/66/86
F01
ADDRESS
DECODER
OUTPUT
BUFFER
DO
93C46/56/57/66/86 F02
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 25056-00 2/98 M-1









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CAT93C56 Даташит, Описание, Даташиты
93C46/56/57/66/86
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature ....................... –65°C to +150°C
Voltage on any Pin with
Respect to Ground(1) ............ –2.0V to +VCC +2.0V
VCC with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100 mA
RELIABILITY CHARACTERISTICS
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
Symbol
Parameter
Min.
Max.
NEND(3)
Endurance
1,000,000
TDR(3)
Data Retention
100
VZAP(3)
ESD Susceptibility
2000
ILTH(3)(4)
Latch-Up
100
D.C. OPERATING CHARACTERISTICS
VCC = +1.8V to +6.0V, unless otherwise specified.
Symbol
ICC1
ICC2
ISB1
ISB2(5)
ILI
ILO
VIL1
VIH1
VIL2
VIH2
VOL1
VOH1
VOL2
VOH2
Parameter
Power Supply Current
(Operating Write)
Power Supply Current
(Operating Read)
Power Supply Current
(Standby) (x8 Mode)
Power Supply Current
(Standby) (x16Mode)
Input Leakage Current
Output Leakage Current
(Including ORG pin)
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
Min.
-0.1
2
0
VCCX0.7
2.4
VCC-0.2
Units
Cycles/Byte
Years
Volts
mA
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
Limits
Typ.
Max.
3
500
10
0
1
1
0.8
VCC+1
VCCX0.2
VCC+1
0.4
0.2
Units
mA
µA
µA
µA
µA
µA
V
V
V
V
V
V
V
Test Conditions
fSK = 1MHz
VCC = 5.0V
fSK = 1MHz
VCC = 5.0V
CS = 0V
ORG=GND
CS=0V
ORG=Float or VCC
VIN = 0V to VCC
VOUT = 0V to VCC,
CS = 0V
4.5VVCC<5.5V
1.8VVCC<2.7V
4.5VVCC<5.5V
IOL = 2.1mA
IOH = -400µA
1.8VVCC<2.7V
IOL = 1mA
IOH = -100µA
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.
(5) Standby Current (ISB2)=0µA (<900nA) for 93C46/56/57/66, (ISB2)=2µA for 93C86.
Doc. No. 25056-00 2/98 M-1
2









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CAT93C56 Даташит, Описание, Даташиты
93C46/56/57/66/86
PIN CAPACITANCE
Symbol
COUT(3)
CIN(3)
Test
OUTPUT CAPACITANCE (DO)
INPUT CAPACITANCE (CS, SK, DI, ORG)
Max.
5
5
Units
pF
pF
Conditions
VOUT=OV
VIN=OV
INSTRUCTION SET
Instruction Device Start Opcode
Type Bit
Address
x8 x16
Data
x8 x16
Comments
READ
93C46
93C56(1)
93C66
93C57
93C86
1
1
1
1
1
10 A6-A0 A5-A0
10 A8-A0 A7-A0
10 A8-A0 A7-A0
10 A7-A0 A6-A0
10 A10-A0 A9-A0
Read Address AN–A0
ERASE
93C46
93C56(1)
93C66
93C57
93C86
1
1
1
1
1
11 A6-A0 A5-A0
11 A8-A0 A7-A0
11 A8-A0 A7-A0
11 A7-A0 A6-A0
11 A10-A0 A9-A0
Clear Address AN–A0
WRITE
93C46
93C56(1)
93C66
93C57
93C86
1
1
1
1
1
01 A6-A0 A5-A0 D7-D0 D15-D0 Write Address AN–A0
01 A8-A0 A7-A0 D7-D0 D15-D0
01 A8-A0 A7-A0 D7-D0 D15-D0
01 A7-A0 A6-A0 D7-D0 D15-D0
01 A10-A0 A9-A0 D7-D0 D15-D0
EWEN
93C46
93C56
93C66
93C57
93C86
1
1
1
1
1
00
11XXXXX
11XXXX
00 11XXXXXXX 11XXXXXX
00 11XXXXXXX 11XXXXXX
00 11XXXXXX 11XXXXX
00 11XXXXXXXXX 11XXXXXXXX
Write Enable
EWDS
93C46
93C56
93C66
93C57
93C86
1
1
1
1
1
00
00XXXXX
00XXXX
00 00XXXXXXX 00XXXXXX
00 00XXXXXXX 00XXXXXX
00 00XXXXXX 00XXXXX
00 00XXXXXXXXX 00XXXXXXXX
Write Disable
ERAL
93C46
93C56
93C66
93C57
93C86
1
1
1
1
1
00
10XXXXX
10XXXX
00 10XXXXXXX 10XXXXXX
00 10XXXXXXX 10XXXXXX
00 10XXXXXX 10XXXXX
00 10XXXXXXXXX 10XXXXXXXX
Clear All Addresses
WRAL
93C46
93C56
93C66
93C57
93C86
1
1
1
1
1
00 01XXXXX 01XXXX D7-D0 D15-D0 Write All Addresses
00 01XXXXXXX 01XXXXXX D7-D0 D15-D0
00 01XXXXXXX 01XXXXXX D7-D0 D15-D0
00 01XXXXXX 01XXXXX D7-D0 D15-D0
00 01XXXXXXXXX 01XXXXXXXX D7-D0 D15-D0
PE(2)
X
I
I
X
X
I
I
Note:
(1) Address bit A8 for 256x8 ORG and A7 for 128x16 ORG are "Don't Care" bits, but must be kept at either a "1" or "0" for READ, WRITE
and ERASE commands.
(2) Applicable only to 93C86
(3) This parameter is tested initially and after a design or process change that affects the parameter.
3 Doc. No. 25056-00 2/98 M-1










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