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PDF NCP1136 Data sheet ( Hoja de datos )
| Número de pieza | NCP1136 | |
| Descripción | High Voltage Switcher | |
| Fabricantes | ON Semiconductor | |
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NCP1136
High Voltage Switcher for
Offline Power Supplies
The NCP1136 switcher integrates a fixed−frequency peak current
mode controller with a low on−resistance, 800 V MOSFET. Available
in a PDIP−7 package, the NCP1136 offers a high level of integration,
including soft−start, frequency−jittering, short−circuit protection,
thermal shutdown protection, frequency foldback mode and
skip−cycle to reduce power consumption in light load condition, peak
current mode control with adjustable internal ramp compensation and
adjustable peak current set point.
During nominal load operation, the part switches at one of the
available frequencies (65 or 100 kHz). When the output power
demand diminishes, the IC automatically enters frequency foldback
mode and provides excellent efficiency at light loads. When the power
demand reduces further, it enters into a skip mode to reduce the
standby consumption down to no load condition.
Protection features include: a timer to detect an overload or a
short−circuit event with auto−recovery or latch protection, and a
built−in VCC overvoltage protection.
The switcher also provides a jittered 65 kHz or 100 kHz switching
frequency to improve the EMI.
Features
• Built−in 800 V, 2.5 A MOSFET with RDS(on) of 3.7 W for NCP1136
• Fixed−Frequency 65 or 100 kHz Current−Mode Control with
Adjustable Internal Ramp Compensation
• Adjustable Current Limit with External Resistor
• Frequency Foldback Down to 26 kHz and Skip−Cycle for Light Load
Efficiency
• Frequency Jittering for EMI Improvement
• Less than 100 mW Standby Power @ High Line
• EPS 2.0 Compliant
• 7−Pin Package Provides Creepage Distance
• These are Pb−Free Devices
http://onsemi.com
PDIP−7
P SUFFIX
CASE 626B
MARKING DIAGRAM
113xyPzzz
AWL
YYWWG
1
x = Specific Device Code
6 = NCP1136
y = A or B
A = Latch
B = Auto−recovery
zzz = Frequency
65 = 65 kHz
100 = 100 kHz
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information on page 12 of
this data sheet.
Table 1. OUTPUT POWER TABLE (Note 1)
230 Vac + 15% (Note 4)
85 − 265 Vac
Product
Adapter (Note 2)
Peak or Open Frame (Note 3)
Adapter (Note 2)
Peak or Open Frame (Note 3)
NCP1136
17 W
34 W
15 W
24 W
1. 12 V output voltage with 135 V reflected output voltage
2. Typical continuous power in a non-ventilated enclosed adaptor measured at 50°C ambient temperature.
3. Maximum practical continuous power in an open-frame design at 50°C ambient temperature
4. 230 VAC or 115 VAC with voltage doubler.
© Semiconductor Components Industries, LLC, 2014
May, 2014 − Rev. 0
1
Publication Order Number:
NCP1126/D
1 page  
NCP1136
Table 5. ELECTRICAL CHARACTERISTICS
(VCC = 12 V, for typical values TJ = 25_C, for min/max values, TJ is –40_C to 125_C, unless otherwise noted)
Characteristics
Conditions
Symbol Min Typ Max Unit
STARTUP AND SUPPLY CIRCUITS
Supply Voltage
Startup Threshold
Minimum Operating Voltage
Operating Hysteresis
VCC Overvoltage Protection Threshold
VCC Overvoltage Protection Filter Delay
VCC Clamp Voltage in Latch Mode
Supply Current
Startup Current
Skip Current
Operating Current at 65 kHz
Operating Current at 100 kHz
Current Consumption in Latch Mode
POWER SWITCH CIRCUIT
VCC increasing
VCC decreasing
VCC(on) − VCC(off)
ICC = 500 mA
VCC = VCC(on) – 0.5 V
VFB = Vskip − 0.1 V
IFB = 50 mA, fSW = 65 kHz
IFB = 50 mA, fSW = 100 kHz
TJ = –40_C to 125_C
VCC(on)
VCC(off)
VCC(HYS)
VCC(OVP)
tOVP(delay)
VZENER
15.75
7.75
6.0
26.3
–
5
ICC1
ICC2
ICC3
ICC4
ICC(latch)
–
–
–
–
42
17
8.5
–
28
26
6.5
–
700
1900
3300
–
20
9.25
–
29.3
–
7.24
15
900
3100
4000
–
V
V
ms
V
mA
mA
Off−State Leakage Current
TJ = 125_C, VDrain = 800 V
IDrain(off)
–
– 20 mA
Breakdown Voltage
TJ = 25_C, IDrain = 250 mA, VFB = 0 V VBR(DSS)
800
–
–
V
ON State Resistance
IDrain = 100 mA
VCC = 10 V, TJ = 25_C
VCC = 10 V, TJ = 125_C
RDS(on) − 3.7 5.0 W
− − 10.0
Output Capacitance
VDS = 25 V, VCC = 0 V, f = 1 MHz
COSS
− 57 − pF
Switching Characteristics
Rise Time
Fall Time
VDS = 400 V, IDrain = 2.5 A,
Vgs = 10 V, Rg = 4.7 W
ns
tr − 7.3 −
tf − 9.2 −
CURRENT SENSE
Current Sense Voltage Threshold
VCS increasing, TJ = 25_C
VCS increasing
VILIM1
VILIM2
730 785 840 mV
720 800 880
Cycle by Cycle Current Sense
Propagation Delay
VCS dv/dt = 1 V/ms, measured from
VILIM1 to DRV falling edge
tCS(delay)
−
100 150
ns
Cycle by Cycle Leading Edge Blanking
Duration
tCS(LEB)
–
320 400
ns
INTERNAL OSCILLATOR
Oscillation Frequency
Maximum Duty Ratio
Frequency Jittering in Percentage of fOSC
FEEDBACK SECTION
65 kHz Version
100 kHz Version
fOSC1
fOSC2
DMAX
fjitter
61 65 71 kHz
92 100 108
78 80 82 %
– ±5 – %
Internal Pull−up Resistor
Equivalent ac resistor from FB to GND
VFB to Internal Current Setpoint
Division Ratio
Rup
Req
Iratio
– 13 – kW
– 15 – kW
–4––
Feedback Voltage Below Which the
Peak Current is Frozen
VFB(freeze)
0.85
1
1.15
V
FREQUENCY FOLDBACK
Frequency Foldback Level on the FB
47% of maximum peak current
VFB(fold) 1.35 1.5 1.78
V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
9. The value is not subjected to production test − verified by design/characterization. The thermal shutdown temperature refers to the junc-
tion temperature of the controller.
http://onsemi.com
5
5 Page 
NCP1136
you de−latch at Vin = 70 Vrms for a minimum voltage of
85 Vrms, you are fine.
VCS
VILIM
max
VCS(fold)
VCS(freeze)
min
VFBV(frFeBe(zfeo)ld3) .2 V
VFB
FSW
fOSC
Frequency
max
ftrans
min
VFB(fold,end) VFB(fold) 3.2 V
VFB
Figure 19. Frequency Foldback Architecture
If it precociously recovers, you will have to increase the
start−up current, unfortunately to the detriment of standby
power.
The most sensitive configuration is actually that of the
half−wave connection proposed in Figure 16. As the current
disappears 5 ms for a 10−ms period (50 Hz input source), the
latch can potentially open at low line. If you really reduce the
start−up current for a low standby power design, you must
ensure enough current in the SCR in case of a faulty event.
An alternate connection to the above is shown in Figure 20:
Figure 20. The Full−wave Connection Ensures
Latch Current Continuity as Well as a
X2−Discharge Path
In this case, the current is no longer made of 5 ms “holes”
and the part can be maintained at a low input voltage.
Experiments show that these 2 MW resistor help to maintain
the latch down to less than 50 V rms, giving an excellent
design margin. Standby power with this approach was also
improved compared to Figure 16 solution. Please note that
these resistors also ensure the discharge of the X2−capacitor
up to a 0.47 mF type.
The de−latch of the SCR occurs when a) the injected
current in the VCC pin falls below the minimum stated in the
data−sheet (32 mA at room temp) or when the part senses a
brown−out recovery.
Auto−Recovery Short−Circuit Protection
In case of output short−circuit or severe overload
situation, an internal error flag is raised and starts a
countdown timer. If the flag is asserted longer than tOVLD,
the driving pulses are stopped and VCC falls down as the
auxiliary pulses are missing. When it hits VCC(off), the
switcher consumption is down to a few mA and the VCC
slowly builds up again by the startup network Rstart, CCC.
When VCC reaches VCC(on), the switcher purposely ignores
the re−start and waits for another VCC cycle: this is the
so−called double hiccup. Illustration of such principle
appears in Figure 21. Please note that soft−start is activated
upon re−start attempt.
VCC(on)
VCC
VCC(off)
drive
time
Figure 21. Auto−Recovery Double Hiccup Sequence
http://onsemi.com
11
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| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet NCP1136.PDF ] | |
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