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PDF W77E058A Data sheet ( Hoja de datos )
| Número de pieza | W77E058A | |
| Descripción | 8-BIT MICROCONTROLLER | |
| Fabricantes | nuvoton | |
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W77E058A Data Sheet
8-BIT MICROCONTROLLER
Table of Contents-
1. GENERAL DESCRIPTION .......................................................................................................... 3
2. FEATURES.................................................................................................................................. 3
3. PIN CONFIGURATIONS ............................................................................................................. 4
4. PIN DESCRIPTION ..................................................................................................................... 5
5. FUNCTIONAL DESCRIPTION .................................................................................................... 7
6. MEMORY ORGANIZATION ........................................................................................................ 9
6.1 Program Memory............................................................................................................. 9
6.2 Data Memory ................................................................................................................... 9
7. SPECIAL FUNCTION REGISTERS .......................................................................................... 11
8. INSTRUCTION .......................................................................................................................... 29
8.1 Instruction Timing .......................................................................................................... 36
8.2 MOVX Instruction .......................................................................................................... 39
8.3 External Data Memory Access Timing .......................................................................... 40
8.4 Wait State Control Signal .............................................................................................. 43
9. POWER MANAGEMENT .......................................................................................................... 44
9.1 Idle Mode....................................................................................................................... 44
9.2 Economy Mode.............................................................................................................. 44
9.3 Power Down Mode ........................................................................................................ 45
10. RESET CONDITIONS ............................................................................................................... 47
10.1 External Reset ............................................................................................................... 47
10.2 Watchdog Timer Reset ................................................................................................. 47
10.3 Reset State.................................................................................................................... 47
11. INTERRUPTS............................................................................................................................ 49
11.1 Interrupt Sources ........................................................................................................... 49
11.2 Priority Level Structure .................................................................................................. 50
11.3 Interrupt Response Time............................................................................................... 52
12. PROGRAMMABLE TIMERS/COUNTERS ................................................................................ 53
12.1 Timer/Counters 0 & 1 .................................................................................................... 53
12.2 Time-base Selection...................................................................................................... 53
12.3 Timer/Counter 2 ............................................................................................................ 56
13. WACHDOG TIMER ................................................................................................................... 60
13.1 Watchdog Control.......................................................................................................... 62
13.2 Clock Control ................................................................................................................. 62
Publication Release Date: April 17, 2007
- 1 - Revision A10
1 page  
W77E058A
4. PIN DESCRIPTION
SYMBOL
EA
TYPE
DESCRIPTIONS
EXTERNAL ACCESS ENABLE: This pin forces the processor to execute out of
I external ROM. It should be kept high to access internal ROM. The ROM address
and data will not be present on the bus if EA pin is high and the program
counter is within 32 KB area. Otherwise they will be present on the bus.
PSEN
ALE
RST
XTAL1
XTAL2
VSS
VDD
P0.0−P0.7
P1.0−P1.7
PROGRAM STORE ENABLE: PSEN enables the external ROM data onto the
O Port 0 address/data bus during fetch and MOVC operations. When internal ROM
access is performed, no PSEN strobe signal outputs from this pin.
O
ADDRESS LATCH ENABLE: ALE is used to enable the address latch that
separates the address from the data on Port 0.
I
RESET: A high on this pin for two machine cycles while the oscillator is running
resets the device.
I
CRYSTAL1: This is the crystal oscillator input. This pin may be driven by an
external clock.
O CRYSTAL2: This is the crystal oscillator output. It is the inversion of XTAL1.
I GROUND: Ground potential
I POWER SUPPLY: Supply voltage for operation.
I/O
PORT 0: Port 0 is an open-drain bi-directional I/O port. This port also provides a
multiplexed low order address/data bus during accesses to external memory.
PORT 1: Port 1 is a bi-directional I/O port with internal pull-ups. The bits have
alternate functions which are described below:
T2(P1.0): Timer/Counter 2 external count input
T2EX(P1.1): Timer/Counter 2 Reload/Capture/Direction control
RXD1(P1.2): Serial port 1 RXD
I/O TXD1(P1.3): Serial port 1 TXD
INT2(P1.4): External Interrupt 2
INT3 (P1.5): External Interrupt 3
INT4(P1.6): External Interrupt 4
INT5 (P1.7): External Interrupt 5
P2.0−P2.7
I/O
PORT 2: Port 2 is a bi-directional I/O port with internal pull-ups. This port also
provides the upper address bits for accesses to external memory.
Publication Release Date: April 17, 2007
- 5 - Revision A10
5 Page 
W77E058A
7. SPECIAL FUNCTION REGISTERS
The W77E058 uses Special Function Registers (SFRs) to control and monitor peripherals and their
Modes.
The SFRs reside in the register locations 80-FFh and are accessed by direct addressing only. Some of
the SFRs are bit addressable. This is very useful in cases where one wishes to modify a particular bit
without changing the others. The SFRs that are bit addressable are those whose addresses end in 0 or
8. The W77E058 contains all the SFRs present in the standard 8052. However, some additional SFRs
have been added. In some cases unused bits in the original 8052 have been given new functions. The
list of SFRs is as follows. The table is condensed with eight locations per row. Empty locations indicate
that there are no registers at these addresses. When a bit or register is not implemented, it will read
high.
Table 1. Special Function Register Location Table
F8 EIP
F0 B
E8 EIE
E0 ACC
D8 WDCON
D0 PSW
C8 T2CON
C0 SCON1
B8 IP
B0 P3
A8 IE
A0 P2
98 SCON0
90 P1
88 TCON
80 P0
T2MOD
SBUF1
SADEN
RCAP2L RCAP2H
ROMMAP
SADEN1
SADDR SADDR1
SBUF
EXIF
TMOD
SP
TL0
DPL
TL1
DPH
TL2
PMR
TH0
DPL1
Note: The SFRs in the column with dark borders are bit-addressable.
TH2
STATUS
P4
TH1
DPH1
CKCON
DPS
TA
PCON
- 11 -
Publication Release Date: April 17, 2007
Revision A10
11 Page | ||
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