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PDF NAU8810 Data sheet ( Hoja de datos )
| Número de pieza | NAU8810 | |
| Descripción | Differential/Mono Audio Codec | |
| Fabricantes | nuvoton | |
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NAU8810
Differential/Mono Audio Codec with 2-wire Interface Control Interface
emPowerAudio™
1. GENERAL DESCRIPTION
The NAU8810 a cost effective low power wideband Monophonic audio CODEC. It is suitable for a wide range of
audio applications, including voice telephony. Supported functions include a 5-band Graphic Equalizer, Automatic
Level Control (ALC) with noise gate, PGA, standard I2S or PCM audio interface, optional PCM time slot
assignment, and a full fractional-N on-chip PLL. This device includes one differential microphone input, and
multiple variable gain control stages in the audio paths. Both a Mono headset/line-level output and a high power
differential BTL speaker driver output are provided.
The analog input path includes a PGA enabling dynamic range optimization of a wide range of input sources with
programmable gain from -12dB to +35.25dB. In addition to a digital high pass filter to remove DC offset voltages,
the ADC also features programmable voice band digital filtering. Audio data is communicated via the audio
interface that supports multiple I2S and PCM data formats. The DAC converter path includes filtering, and mixing,
programmable-gain amplifiers, and soft muting. The 2-Wire digital control interface has an independent supply
voltage to enable easy integration into multiple supply voltage systems. The NAU88U10 operates at supply
voltages from 2.5V to 3.6V, and the digital core can operate at a voltage as low as 1.71V to conserve power.
The NAU8810 is specified for operation from -40C to +85C, and is available with automotive AEC-Q100
qualification. Please refer to ordering information for AEC-Q100 compliance part number.
2. FEATURES
24-bit signal processing linear Audio CODEC
Audio DAC: 93dB SNR and -84dB THD
Audio ADC: 91dB SNR and -79dB THD
Support variable sample rates from 8 - 48kHz
Analog I/O
Integrated programmable Microphone Amplifier
Integrated BTL Speaker Driver 1 W (8Ω / 5V)
Earphone / Speaker / Line-Output Mixing / Routing
Integrated Headset Driver 40mW (16Ω / 3.3V)
Low Noise bias supply voltage for microphone
On-chip full fractional-N PLL
Interfaces
I2S digital interface PCM time slot assignment
2-Wire serial control Interface (I2C style; /Write capable)
emPowerAudio™
Datasheet Revision 2.8
Page 1 of 102
March 1, 2017
1 page  
5. BLOCK DIAGRAM
NAU8810
VSSSPK
VSSD
VSSA
VDDSPK
VSSD
VDDA
MCLK
SCLK
SDIO
ADCOUT
DACIN
FS
BCLK
Figure 2: NAU88U10 General Block Diagram
emPowerAudio™
Datasheet Revision 2.8
Page 5 of 102
March 1, 2017
5 Page 
NAU8810
8. List of Tables
Table 1: Pin Description ................................................................................................................................................4
Table 2: Register associated with Input PGA Control .................................................................................................18
Table 3: Microphone Non-Inverting Input Impedances.................................................................................................19
Table 4: Microphone Inverting Input Impedances .......................................................................................................19
Table 5: Registers associated with ALC and Input PGA Gain Control ........................................................................20
Table 6: Registers associated with PGA Boost Stage Control ....................................................................................20
Table 7: Register associated with Microphone Bias....................................................................................................21
Table 8: Microphone Bias Voltage Control ..................................................................................................................22
Table 9: Register associated with ADC .......................................................................................................................23
Table 10: High Pass Filter Cut-off Frequencies (HPFAM=1).......................................................................................23
Table 11: Registers associated with Notch Filter Function..........................................................................................24
Table 12: Equations to Calculate Notch Filter Coefficients..........................................................................................24
Table 13: Register associated with ADC Gain ............................................................................................................24
Table 14: Registers associated with ALC Control .......................................................................................................27
Table 15: ALC Maximum and Minimum Gain Values ..................................................................................................27
Table 16: Registers associated with DAC Gain Control ..............................................................................................32
Table 17: Registers associated with Equalizer Control ...............................................................................................35
Table 18: Speaker Output Controls.............................................................................................................................37
Table 19: MONO Output Controls ...............................................................................................................................37
Table 20: General Purpose Control.............................................................................................................................41
Table 21: Registers associated with PLL ....................................................................................................................42
Table 22: Registers associated with PLL ....................................................................................................................43
Table 23: PLL Frequency Examples ...........................................................................................................................44
Table 24: Standard Interface modes ...........................................................................................................................48
Table 25: Audio Interface Control Registers................................................................................................................48
Table 26: Companding Control ...................................................................................................................................53
Table 27: Power up sequence.....................................................................................................................................56
Table 28: Power down Sequence ...............................................................................................................................57
Table 29: Registers associated with Power Saving.....................................................................................................57
Table 30: VDDA 3.3V Supply Current .........................................................................................................................58
Table 31: 2-WireTiming Parameters ...........................................................................................................................88
Table 32: Audio Interface Timing Parameters .............................................................................................................92
Table 33: MCLK Timing Parameter .............................................................................................................................92
emPowerAudio™
Datasheet Revision 2.8
Page 11 of 102
March 1, 2017
11 Page | ||
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