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PDF NCT3101S Data sheet ( Hoja de datos )
| Número de pieza | NCT3101S | |
| Descripción | Bus Termination Regulator | |
| Fabricantes | novoTon | |
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Nuvoton
Bus Termination Regulator
NCT3101S
DATE: MARCH, 2013
Revision: A4
1 page  
NCT3101S
5. PIN DESCRIPTION
SYMBOL
VIN
PIN
1
VREF
3
VOUT
VCNTL
4
6
GND
NC
2
5, 7, 8
I/O FUNCTION
Main power input pin which supplies current to output pin. For
I lower power dissipation consideration, using VDDQ (Supply
voltage for DRAM) as power source is recommended.
Internal reference voltage source. Generally, VREF tracks
VDDQ/2 for DDR application.
Using voltage dividing resistors and capacitor as low pass
I
filter for noise immunity and output voltage soft start is
recommended.
If using an N-MOSFET as shutdown function, please make
sure the sinking current capability can pull down VREF under
0.2V.
O
Voltage output pin which is regulated to track VREF voltage.
Connect to VTT power rail of DDR-SDRAM DIMM.
Power for internal control logic circuitry. A ceramic decoupling
I
capacitor with 0.1uF is required. The voltage on this pin must
be at least 2V greater than output voltage and no less than
minimum VCNTL supply voltage.
Ground.
Connect to negative terminal of the output capacitor(s).
No connection.
6. FUNCTIONAL DESCRIPTION
VTT Sink/Source Regulator
The NCT3101S is a sink/source tracking termination regulator specifically designed for low input
voltage, low cost and low external component count systems where space is a key application
parameter. The NCT3101S integrates a high performance, low dropout linear regulator that is
capable of both sinking and sourcing current. The load dropout regulator employs a fast
feedback loop so that small ceramic capacitors can be used to support the fast load transient
response. The NCT3101S also incorporates two distinct power rails that separates the analog
circuitry from the power output stage. This allows a split rail approach to be utilized to decrease
internal power dissipation.
Series Stub Termination Logic (SSTL) was created to improve signal integrity of the data
transmission across the memory bus. This termination scheme is essential to prevent data error
from signal reflections while transmitting at high frequencies encountered with DDR-SDRAM.
The DDR-SDRAM memory termination structure determines the main characteristics of the VT
rail, which is to be able to sink and source current while maintaining acceptable VTT tolerance.
Fig. 6-1 shows typical characteristics for a single memory cell.
When Q1 is on and Q2 is off:
Current flows from VDDQ via the termination resistor to VTT
VTT sinks current
Publication Date: Mar., 2013
-3- Revision A4
5 Page 
NCT3101S
8. TYPICAL OPERATING CHARACTERISTICS AND WAVEFORMS
Operating Characteristics
VOS vs. Temperature, VCNTL=3.3V
0.80
0.70
0.60
IOUT = 0mA
0.50
0.40
0.30
0.20
0.10
DDR1
DDR2
DDR3
0.00
-40 -20
0 20 40 60 80 100 120
Temperature (°C)
VOS vs. Temperature, VCNTL=5V
0.90
0.80
0.70
0.60
0.50
0.40
0.30
0.20
0.10
0.00
-40
IOUT = 0mA
-20 0 20 40 60 80
Temperature (°C)
DDR1
DDR2
DDR3
100 120
VCNTL Current vs. Temperature
0.90
0.80
0.70
VCNTL=3.3V
IOUT = 0mA
0.60
0.50
0.40
0.30
0.20
0.10
DDR1
DDR2
DDR3
0.00
-40 -20
0 20 40 60 80 100 120
Temperature (°C)
VCNTL Current vs. Temperature
0.90
0.80
0.70
0.60
0.50
0.40
0.30
0.20
0.10
0.00
-40
VCNTL=5V
IOUT = 0mA
DDR1
DDR2
DDR3
-20 0 20 40 60 80
Temperature (°C)
100 120
Publication Date: Mar., 2013
-9- Revision A4
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet NCT3101S.PDF ] | |
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