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PDF AD5405 Data sheet ( Hoja de datos )
| Número de pieza | AD5405 | |
| Descripción | Dual 12-Bit/ High Bandwidth/ Multiplying DAC with 4-Quadrant Resistors and Parallel Interface | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Dual 12-Bit, High Bandwidth, Multiplying DAC with
4-Quadrant Resistors and Parallel Interface
FEATURES
On chip 4-quadrant resistors allow flexible output ranges
10 MHz multiplying bandwidth
Fast parallel interface write cycle: 58 MSPS
2.5 V to 5.5 V supply operation
±10 V reference input
Extended temperature range: −40°C to 125°C
40-lead LFCSP package
Guaranteed monotonic
4-quadrant multiplication
Power-on reset
Readback function
.5 µA typical current consumption
APPLICATIONS
Portable battery-powered applications
Waveform generators
Analog processing
Instrumentation applications
Programmable amplifiers and attenuators
Digitally-controlled calibration
Programmable filters and oscillators
Composite video
Ultrasound
Gain, offset, and voltage trimming
AD5405
GENERAL DESCRIPTION
The AD54051 is a dual CMOS, 12-bit, current output digital-
to-analog converter (DAC).This device operates from a 2.5 V to
5.5 V power supply, making it suited to battery-powered and
other applications.
The applied external reference input voltage (VREF) determines
the full-scale output current. An integrated feedback resistor
(RFB) provides temperature tracking and full-scale voltage
output when combined with an external I-to-V precision
amplifier. This device also contains all the 4-quadrant resistors
necessary for bipolar operation and other configuration modes.
This DAC utilizes data readback, allowing the user to read the
contents of the DAC register via the DB pins. On power-up, the
internal register and latches are filled with zeros and the DAC
outputs are at zero scale.
As a result of manufacture with a CMOS submicron process, the
device offers excellent 4-quadrant multiplication characteristics,
with large signal multiplying bandwidths of up to 10 MHz.
The AD5405 has a 6 mm × 6 mm, 40-lead LFCSP package.
1 US Patent Number 5,689,257.
VDD
DATA
INPUTS
DB0
DB11
AD5405
R3A R2_3A R2A
R3 R2
2R 2R
VREFA R1A
R1
2R
RFB
2R
INPUT
BUFFER
LATCH
12-BIT
R-2R DAC A
RFBA
IOUT1A
IOUT2A
DAC A/B
CS
R/W
LDAC
GND
CONTROL
LOGIC
LATCH
12-BIT
R-2R DAC B
POWER-ON
RESET
R3 R2
2R 2R
R1
2R
R3B R2_3B R2B VREFB R1B
RFB
2R
Figure 1. AD5405 Functional Block Diagram
IOUT1B
IOUT2B
RFB B
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
1 page  
AD5405
TIMING CHARACTERISTICS
VDD = 2.5 V to 5.5 V, VREF = 5 V, IOUT2 = 0 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter1, 2
Write Mode
t1
t2
t3
t4
t5
t6
t7
t8
t9
Data Readback Mode
t10
t11
t12
t13
Limit at TMIN, TMAX
0
0
10
10
0
6
0
5
7
0
0
5
35
5
10
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns typ
ns typ
ns typ
ns max
ns typ
ns max
Conditions/Comments
R/W to CS setup time
R/W to CS hold time
CS low time
Address setup time
Address hold time
Data setup time
Data hold time
R/W high to CS low
CS min high time
Address setup time
Address hold time
Data access time
Bus relinquish time
1 See Figure 2. Temperature range for Y version is −40°C to +125°C. Guaranteed by design and characterization, not subject to production test.
2 All input signals are specified with tr = tf = 5ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. Digital output timing measured
with load circuit in Figure 3.
R/W
CS
DACA/DACB
DATA
t1 t2 t8
t3
t4
t9
t5 t10
t2
t11
t6
DATA VALID
t7
Figure 2. Timing Diagram
t12 t13
DATA VALID
200µA
IOL
TO
OUTPUT
PIN
CL
50pF
200µA
IOH
VOH (MIN) + VOL (MAX)
2
Figure 3. Load Circuit for Data Timing Specifications
Rev. 0 | Page 5 of 24
5 Page 
0
TA = 25°C
–10
VDD = 5V
AMP = AD8038
AD5405
–20 65k CODES
–30
–40
–50
–60
–70
–80
–90
0 2 4 6 8 10 12
FREQUENCY (MHz)
Figure 23. Wideband SFDR, fOUT = 100 kHz, Clock = 25 MHz
0 TA= 25°C
–10 VDD = 5V
AMP = AD8038
–20
AD5405
65k CODES
–30
–40
–50
–60
–70
–80
–90
–100
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
FREQUENCY (MHz)
Figure 24. Wideband SFDR, fOUT =500 kHz, Clock = 10 MHz
0
TA = 25°C
–10
VDD = 5V
AMP = AD8038
AD5405
–20 65k CODES
–30
–40
–50
–60
–70
–80
–90
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
FREQUENCY (MHz)
Figure 25. Wideband SFDR, fOUT = 50 kHz, Clock = 10 MHz
AD5405
0 TA= 25°C
–10 VDD = 3V
AMP = AD8038
–20 AD5405
65k CODES
–30
–40
–50
–60
–70
–80
–90
–100
250 300 350 400 450 500 550 600 650 700 750
FREQUENCY (MHz)
Figure 26. Narrow-Band Spectral Response, fOUT = 500 kHz, Clock = 25 MHz
20
TA= 25°C
VDD = 3V
0 AMP = AD8038
AD5405
65k CODES
–20
–40
–60
–80
–100
–120
50 60 70 80 90 100 110 120 130 140 150
FREQUENCY (MHz)
Figure 27. Narrow-Band SFDR, fOUT = 100 kHz, Clock = 25 MHz
0
TA= 25°C
–10 VDD = 3V
AMP = AD8038
–20 AD5405
65k CODES
–30
–40
–50
–60
–70
–80
–90
–100
70 75 80 85 90 95 100 105 110 115 120
FREQUENCY (MHz)
Figure 28. Narrow-Band IMD, fOUT = 90 kHz, 100 kHz, Clock = 10 MHz
Rev. 0 | Page 11 of 24
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet AD5405.PDF ] | |
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