93LCS66-ISN PDF даташит
Спецификация 93LCS66-ISN изготовлена «Microchip Technology» и имеет функцию, называемую «2K/4K 2.5V Microwire Serial EEPROM with Software Write Protect». |
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Детали детали
Номер произв | 93LCS66-ISN |
Описание | 2K/4K 2.5V Microwire Serial EEPROM with Software Write Protect |
Производители | Microchip Technology |
логотип |
12 Pages
No Preview Available ! |
93LC66A/B
4K 2.5V Microwire® Serial EEPROM
FEATURES
• Single supply with operation down to 2.5V
• Low power CMOS technology
- 1 mA active current (typical)
- 1 µA standby current (maximum)
• 512 x 8 bit organization (93LC66A)
• 256 x 16 bit organization (93LC66B)
• Self-timed ERASE and WRITE cycles
(including auto-erase)
• Automatic ERAL before WRAL
• Power on/off data protection circuitry
• Industry standard 3-wire serial interface
• Device status signal during ERASE/WRITE cycles
• Sequential READ function
• 1,000,000 E/W cycles guaranteed
• Data retention > 200 years
• 8-pin PDIP/SOIC and 8-pin TSSOP packages
• Available for the following temperature ranges:
- Commercial (C):
- Industrial (I):
0°C to +70°C
-40°C to +85°C
PACKAGE TYPE
DIP
SOIC
BLOCK DIAGRAM
MEMORY
ARRAY
ADDRESS
DECODER
DI
CS
CLK
DATA
REGISTER
ADDRESS
COUNTER
OUTPUT
BUFFER
DO
MODE
DECODE
LOGIC
CLOCK
GENERATOR
Vcc
Vss
DESCRIPTION
The Microchip Technology Inc. 93LC66A/B are 4K-bit,
low voltage serial Electrically Erasable PROMs. The
device memory is configured as x8 (93LC66A) or
x16 bits (93LC66B). Advanced CMOS technology
makes these devices ideal for low power nonvolatile
memory applications. The 93LC66A/B is available in
standard 8-pin DIP, surface mount SOIC, and TSSOP
packages. The 93LC66AX/BX are only offered in a
150-mil SOIC package.
SOIC
TSSOP
CS 1
CLK 2
DI 3
DO 4
8 Vcc
CS
7 NC
CLK
6 NC
DI
5 Vss
DO
1
2
3
4
8 VCC
NC 1
7 NC
Vcc 2
6 NC
CS 3
5 Vss CLK 4
CS 1
8 NC CLK 2
DI 3
7 Vss
DO 4
6 DO
5 DI
8 Vcc
7 NC
6 NC
5 Vss
Microwire is a registered trademark of Motorola.
1998 Microchip Technology Inc.
DS21209C-page 1
No Preview Available ! |
93LC66A/B
1.0 ELECTRICAL
CHARACTERISTICS
1.1 Maximum Ratings*
Vcc ...................................................................................7.0V
All inputs and outputs w.r.t. Vss ............... -0.6V to Vcc +1.0V
Storage temperature .....................................-65°C to +150°C
Ambient temp. with power applied ................-65°C to +125°C
Soldering temperature of leads (10 seconds) ............. +300°C
ESD protection on all pins................................................4 kV
*Notice: Stresses above those listed under “Maximum ratings” may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is
not implied. Exposure to maximum rating conditions for extended peri-
ods may affect device reliability.
TABLE 1-1 PIN FUNCTION TABLE
Name
Function
CS
CLK
DI
DO
VSS
NC
VCC
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
No Connect
Power Supply
TABLE 1-2 DC AND AC ELECTRICAL CHARACTERISTICS
All parameters apply over the specified Commercial (C):
operating ranges unless otherwise
Industrial (I):
noted
VCC = +2.5V to +6.0V
VCC = +2.5V to +6.0V
Tamb = 0°C to +70°C
Tamb = -40°C to +85°C
Parameter
Symbol
Min.
Max.
Units
Conditions
High level input voltage
VIH1
VIH2
2.0
0.7 VCC
Vcc +1
Vcc +1
V 2.7V ≤ VCC ≤ 6.0V (Note 2)
V VCC < 2.7V
Low level input voltage
VIL1
VIL2
-0.3 0.8
-0.3 0.2 Vcc
V VCC > 2.7V (Note 2)
V VCC < 2.7V
Low level output voltage
VOL1
VOL2
—
—
0.4
0.2
V IOL = 2.1 µA; Vcc = 4.5V
V IOL =100 µA; Vcc = Vcc Min.
High level output voltage
VOH1
VOH2
2.4
VCC-0.2
—
—
V IOH = -400 µA; Vcc = 4.5V
V IOH = -100 µA; Vcc = Vcc Min.
Input leakage current
ILI -10 10
µA VIN = VSS to VCC
Output leakage current
ILO -10 10
µA VOUT = VSS to VCC
Pin capacitance
(all inputs/outputs)
CIN, COUT
—
7
pF
VIN/VOUT = 0 V (Notes 1 & 2)
Tamb = +25°C, FCLK = 1 MHz
Operating current
ICC read
ICC write
—
—
1
500
1.5
mA FCLK = 2 MHz; Vcc = 6.0V
µA FCLK = 1 MHz; Vcc = 3.0V
mA
Standby current
ICCS
—
1
µA CS = Vss; DI = VSS
Clock frequency
FCLK
—
2
1
MHz
MHz
VCC > 4.5V
VCC < 4.5V
Clock high time
TCKH
250
—
ns
Clock low time
TCKL
250
—
ns
Chip select setup time
TCSS
50
—
ns Relative to CLK
Chip select hold time
TCSH
0
—
ns Relative to CLK
Chip select low time
TCSL
250
—
ns
Data input setup time
TDIS
100
—
ns Relative to CLK
Data input hold time
TDIH
100
—
ns Relative to CLK
Data output delay time
TPD — 400
ns CL = 100 pF
Data output disable time
TCZ — 100
ns CL = 100 pF (Note 2)
Status valid time
TSV — 500
ns CL = 100 pF
TWC
—
6
ms ERASE/WRITE mode
Program cycle time
TEC —
6
ms ERAL mode
TWL —
15
ms WRAL mode
Endurance
— 1M —
cycles
25°C, VCC = 5.0V, Block Mode (Note 3)
Note 1:
2:
3:
This parameter is tested at Tamb = 25°C and Fclk = 1 MHz.
This parameter is periodically sampled and not 100% tested.
This application is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total
Endurance Model which may be obtained on our website.
DS21209C-page 2
1998 Microchip Technology Inc.
No Preview Available ! |
93LC66A/B
2.0 PIN DESCRIPTION
2.1 Chip Select (CS)
A high level selects the device; a low level deselects the
device and forces it into standby mode. However, a pro-
gramming cycle which is already in progress will be
completed, regardless of the Chip Select (CS) input
signal. If CS is brought low during a program cycle, the
device will go into standby mode as soon as the pro-
gramming cycle is completed.
CS must be low for 250 ns minimum (TCSL) between
consecutive instructions. If CS is low, the internal con-
trol logic is held in a RESET status.
2.2 Serial Clock (CLK)
The Serial Clock (CLK) is used to synchronize the com-
munication between a master device and the 93LC66A/
B. Opcode, address, and data bits are clocked in on the
positive edge of CLK. Data bits are also clocked out on
the positive edge of CLK.
CLK can be stopped anywhere in the transmission
sequence (at high or low level) and can be continued
anytime with respect to clock high time (TCKH) and
clock low time (TCKL). This gives the controlling master
freedom in preparing opcode, address, and data.
CLK is a “Don't Care” if CS is low (device deselected).
If CS is high, but a START condition has not been
detected, any number of clock cycles can be received
by the device without changing its status (i.e., waiting
for a START condition).
CLK cycles are not required during the self-timed
WRITE (i.e., auto ERASE/WRITE) cycle.
After detection of a START condition the specified num-
ber of clock cycles (respectively low to high transitions
of CLK) must be provided. These clock cycles are
required to clock in all required opcode, address, and
data bits before an instruction is executed (Table 2-1
and Table 2-2). CLK and DI then become don't care
inputs waiting for a new START condition to be
detected.
2.3 Data In (DI)
Data In (DI) is used to clock in a START bit, opcode,
address, and data synchronously with the CLK input.
2.4 Data Out (DO)
Data Out (DO) is used in the READ mode to output
data synchronously with the CLK input (TPD after the
positive edge of CLK).
This pin also provides READY/BUSY status information
during ERASE and WRITE cycles. READY/BUSY sta-
tus information is available on the DO pin if CS is
brought high after being low for minimum chip select
low time (TCSL) and an ERASE or WRITE operation
has been initiated.
The status signal is not available on DO, if CS is held
low during the entire ERASE or WRITE cycle. In this
case, DO is in the HIGH-Z mode. If status is checked
after the ERASE/WRITE cycle, the data line will be high
to indicate the device is ready.
TABLE 2-1
Instruction
ERASE
ERAL
EWDS
EWEN
READ
WRITE
WRAL
INSTRUCTION SET FOR 93LC66A
SB Opcode
Address
1 11 A8 A7 A6 A5 A4 A3 A2 A1 A0
1 00 1 0 X X X X X X X
1 00 0 0 X X X X X X X
1 00 1 1 X X X X X X X
1 10 A8 A7 A6 A5 A4 A3 A2 A1 A0
1 01 A8 A7 A6 A5 A4 A3 A2 A1 A0
1 00 0 1 X X X X X X X
Data In
—
—
—
—
—
D7 - D0
D7 - D0
Data Out
(RDY/BSY)
(RDY/BSY)
HIGH-Z
HIGH-Z
D7 - D0
(RDY/BSY)
(RDY/BSY)
Req. CLK Cycles
12
12
12
12
20
20
20
TABLE 2-2 INSTRUCTION SET FOR 93LC66B
Instruction SB Opcode
Address
Data In
ERASE
ERAL
EWDS
EWEN
READ
WRITE
WRAL
1
1
1
1
1
1
1
11 A7 A6 A5 A4 A3 A2 A1 A0
—
00 1 0 X X X X X X
—
00 0 0 X X X X X X
—
00 1 1 X X X X X X
—
10 A7 A6 A5 A4 A3 A2 A1 A0
—
01 A7 A6 A5 A4 A3 A2 A1 A0 D15 - D0
00 0 1 X X X X X X D15 - D0
Data Out
(RDY/BSY)
(RDY/BSY)
HIGH-Z
HIGH-Z
D15 - D0
(RDY/BSY)
(RDY/BSY)
Req. CLK Cycles
11
11
11
11
27
27
27
1998 Microchip Technology Inc.
DS21209C-page 3
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Номер в каталоге | Описание | Производители |
93LCS66-ISL | 2K/4K 2.5V Microwire Serial EEPROM with Software Write Protect | Microchip Technology |
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93LCS66-ISN | 2K/4K 2.5V Microwire Serial EEPROM with Software Write Protect | Microchip Technology |
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