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PDF HMP8116CN Data sheet ( Hoja de datos )
| Número de pieza | HMP8116CN | |
| Descripción | NTSC/PAL Video Decoder | |
| Fabricantes | Intersil Corporation | |
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SEMICONDUCTOR
HMP8116
ADVANCE DRAFT
April 1998
NTSC/PAL Video Decoder
Features
• (M) NTSC and (B, D, G, H, I, M, N, NC) PAL Operation
- Optional Auto Detect of Video Standard
- ITU-R BT.601(CCIR601) and Square Pixel Operation
• Digital Output Formats
- VMI Compatible
- 8-bit, 16-bit 4:2:2 YCbCr
- 15-bit (5,5,5), 16-bit (5,6,5) RGB
- Linear or Gamma-Corrected
- 8-bit BT.656
• Analog Input Formats
- Three Analog Composite Inputs
- Analog Y/C (S-video) Input
• “Raw” (Oversampled) VBI Data Capture
• “Sliced” VBI Data Capture Capabilities
- Closed Captioning
- Widescreen Signalling (WSS)
- BT.653 System B, C and D Teletext
- NABTS (North American Broadcast Teletext)
- WST (World System Teletext)
• 2-Line (1H) Comb Filter Y/C Separator
• Fast I2C Interface
• Two 8-Bit ADCs
Description
The HMP8115 is a high quality NTSC and PAL decoder with
internal A/D converters. It is compatible with NTSC M, PAL
B, D, G, H, I, M, N, and combination N (NC) video standards.
Both composite and S-video (Y/C) input formats are sup-
ported. A 2-line comb filter plus a user-selectable chromi-
nance trap filter provide high quality Y/C separation. User
adjustments include brightness, contrast, saturation, hue,
and sharpness.
Data during the vertical blanking interval (VBI), such as
closed captioning, widescreen signalling and teletext, may
be captured and output as BT.656 ancillary data. Closed
captioning and widescreen signalling information may also
be read out via the I2C interface.
Ordering Information
TEMP.
PART NUMBER RANGE (oC) PACKAGE
PKG.NO.
HMP8116CN
0 to 70 80 Ld PQFP Q80.14x20
HMPVIDEVAL/ISA Evaluation Board: ISA Frame Grabber
NOTES:
1. PQFP is also known as QFP and MQFP.
2. Evaluation Board and Reference Design descriptions are in the
Applications section.
Applications
• Multimedia PCs
• Video Conferencing
• Video Compression Systems
• Video Security Systems
• LCD Projectors and Overhead Panels
• Related Products
- NTSC/PAL Encoders: HMP815x, HMP817x
- NTSC/PAL Decoders: HMP8112A
• Related Literature
- AN9644: Composite Video Separation Techniques
- AN9716: Widescreen Signalling
- AN9717: YCbCr to RGB Considerations
- AN9728: BT.656 Video Interface for ICs
- AN9738: VMI Video Interface for ICs
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1998
1
File Number 4510
1 page  
HMP8116
Introduction
The HMP8116 is designed to decode baseband composite
or S-video NTSC and PAL signals, and convert them to
either digital YCbCr or RGB data. In addition to performing
the basic decoding operations, the HMP8116 includes hard-
ware to decode different types of VBI data and to generate
digital video patterns for a blue screen, black screen and full
screen color bars.
The digital PLLs are designed to synchronize to all NTSC
and PAL standards. A chroma PLL is used to maintain
chroma lock for demodulation of the color information; a line-
locked PLL is used to maintain vertical spatial alignment.
The PLLs are designed to maintain lock even in the event of
VCR headswitches and multipath noise.
The HMP8116 contains two 8-bit A/D converters and an I2C
interface for programming internal registers
External Video Processing
Before a video signal can be digitized the decoder has some
external processing considerations that need to be
addressed. This section discusses those external aspects of
the HMP8116.
ANALOG VIDEO INPUTS
The HMP8116 supports either three composite or two com-
posite and one S-video input.
Three analog video inputs (CVBS 1-3) are used to select
which one of three composite video sources are to be
decoded. To support S-video applications, the Y channel
drives the CVBS 3 analog input, and the C channel drives
the C analog input.
The analog inputs must be AC-coupled to the video signals,
as shown in the Applications section.
toration” section. After digitization, sample rate converters and
a comb filter are used to perform color separation and demod-
ulation.
A/D CONVERSION
Video data is sampled at the CLK2 frequency then pro-
cessed by the input sample rate converter. The output levels
of the ADC after AGC and DC restoration processing are:
(M) NTSC
(M, N) PAL
(B, D, G, H, I, NC)
PAL
white
black
blank
sync
196
66
56
0
196
59
59
0
AGC AND DC RESTORATION
The AGC amplifier attenuates or amplifies the analog video
signal to ensure that the blank level generates code 56 or 59
depending on the video standard. The difference from the
ideal blank level of 56 or 59 is used to control the amount of
attenuation or gain of the analog video signal.
DC restoration positions the video signal so that the sync tip
generates a code 0. The internal timing windows for AGC
and DC Restoration are show in Figure 3.
VIDEO INPUT
AGC
ANTI-ALIASING FILTERS
An external anti-alias filter is required to achieve optimum
performance and prevent high frequency components from
being aliased back into the video image.
For the CVBS 1-3 inputs, a single filter is connected between
the YOUT and YIN pins. For the C input, the antialiasing filter
should be connected before the C input. A recommended fil-
ter is shown in Figure 1.
YOUT
R1
332
C1
33pF
L1
8.2uH
C2
82pF
YIN
R2
4.02K
FIGURE 1. RECOMMENDED ANTI-ALIASING FILTER
Digitization of Video
Prior to A/D conversion, the video signal is DC restored and
gained to generate known video levels into the digital process-
ing logic. This process is addessed in the “AGC and DC Res-
DC RESTORE
FIGURE 2. AGC AND DC RESTORE INTERNAL TIMING
INPUT SIGNAL DETECTION
It is assumed there is no video input if a horizontal sync is
not detected for 16 consecutive lines. When no video has
been detected, nominal video timing is generated for the
previously detected or programmed video standard. A
maskable interrupt is included to flag when no video has
been detected (bit 6 of the INTERRUPT MASK register 0FH)
allowing for blue/black/color bar output modes to be enabled
if desired. The vertical sync interrupt can be used in deter-
mining when a video signal is present on the currently
selected video mux input. Bit 0 of register 0FH is used to
enable vertical sync interrupts.
5
5 Page 
HMP8116
NTSC M
PAL B, D, G, H, I, N, NC
LINES 1 - 22 NOT ACTIVE
240 ACTIVE LINES
PER FIELD
(LINES 23-262)
480 ACTIVE
LINES / FRAME
(NTSC, PAL M) LINES 263 - 284 NOT ACTIVE
240 ACTIVE LINES
PER FIELD
(LINES 285 - 524)
LINE 525
NOT ACTIVE
TOTAL PIXELS
ACTIVE PIXELS
ODD FIELD
SYNC AND
BACK
PORCH
VERTICAL
BLANKING
EVEN FIELD
LINES 1 - 22 NOT ACTIVE
288 ACTIVE LINES
PER FIELD
(LINES 23 - 310)
LINES 311 - 335 NOT ACTIVE
576 ACTIVE
LINES / FRAME
(PAL)
FRONT
PORCH
NUMBER OF PIXELS
RECTANGULAR (SQUARE)
NTSC
PAL
858 (780)
720 (640)
864 (944)
720 (768)
288 ACTIVE LINES
PER FIELD
(LINES 336 - 623)
LINES 624-625
NOT ACTIVE
TOTAL PIXELS
ACTIVE PIXELS
NOTE:
7. The line numbering for PAL (M) followings NTSC (M) line count minus 3 per the video standards.
FIGURE 8. TYPICAL ACTIVE VIDEO REGIONS
TABLE 3. PIXEL OUTPUT FORMATS
PIN NAME
8-BIT, 4:2:2, YCbCr
16-BIT, 4:2:2, YCbCr 15-BIT, RGB, (5,5,5) 16-BIT, RGB, (5,6,5)
BT.656
P0
0 [0]
Cb0, Cr0 [D0n+1]
B0 [D0n+1]
B0 [D0n+1]
0 [0]
P1
0 [0]
Cb1, Cr1 [D1n+1]
B1 [D1n+1]
B1 [D1n+1]
0 [0]
P2
0 [0]
Cb2, Cr2 [D2n+1]
B2 [D2n+1]
B2 [D2n+1]
0 [0]
P3
0 [0]
Cb3, Cr3 [D3n+1]
B3 [D3n+1]
B3 [D3n+1]
0 [0]
P4
0 [0]
Cb4, Cr4 [D4n+1]
B4 [D4n+1]
B4 [D4n+1]
0 [0]
P5
0 [0]
Cb5, Cr5 [D5n+1]
G0 [D5n+1]
G0 [D5n+1]
0 [0]
P6
0 [0]
Cb6, Cr6 [D6n+1]
G1 [D6n+1]
G1 [D6n+1]
0 [0]
P7
0 [0]
Cb7, Cr7 [D7n+1]
G2 [D7n+1]
G2 [D7n+1]
0 [0]
P8 Y0, Cb0, Cr0 [D0]
P9 Y1, Cb1, Cr1 [D1]
P10 Y2, Cb2, Cr2 [D2]
P11 Y3, Cb3, Cr3 [D3]
P12 Y4, Cb4, Cr4 [D4]
P13 Y5, Cb5, Cr5 [D5]
P14 Y6, Cb6, Cr6 [D6]
P15 Y7, Cb7, Cr7 [D7]
Y0 [D0n]
Y1 [D1n]
Y2 [D2n]
Y3 [D3n]
Y4 [D4n]
Y5 [D5n]
Y6 [D6n]
Y7 [D7n]
G3 [D0n]
G4 [D1n]
R0 [D2n]
R1 [D3n]
R2 [D4n]
R3 [D5n]
R4 [D6n]
0 [D7n]
G3 [D0n]
G4 [D1n]
G5 [D2n]
R0 [D3n]
R1 [D4n]
R2 [D5n]
R3 [D6n]
R4 [D7n]
YCbCr Data,
Ancillary Data,
SAV and EAV
Sequences
[D0 - D7, where
P8 corresponds
to D0]
NOTE:
8. Definitions in brackets are port definitions during raw VBI data transfers. Refer to the section on teletext for more information on raw VBI.
PIXEL OUTPUT PORT
Pixel data is output via the P0-P15 pins. Refer to Table 3 for
the output pin definition as a function of the output mode.
8-BIT YCbCr OUTPUT
The DVALID output pin may be configured to operate in one
of two ways. The configuration is determined by the
DVLD_LTC bit (bit 4) of the GENLOCK CONTROL register
04H.
If DVLD_LTC=0, the DVALID output is continuously asserted
during the entire active video time on active scan lines if CLK2
is exactly 2x the desired output sample rate. DVALID being
asserted indicates valid pixel data is present on the P15-P8
pixel outputs. DVALID is never asserted during the blanking
intervals. Refer to Figure 9.
If DLVD_LTC=1, DVALID has the same internal timing as the
first mode, but is ANDed with the CLK2 signal, and the result
is output onto the DVALID pin. This results in a gated CLK2
signal being output during the active video time on active
scan lines. Refer to Figure 10.
If 8-bit YCbCr data is generated, it is output following each
rising edge of CLK2. The YCbCr data is multiplexed as [Cb Y
Cr Y′ Cb Y Cr Y′...], with the first active data each scan line
containing Cb data. The pixel output timing is shown in Fig-
11
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