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PDF HMP8191CN Data sheet ( Hoja de datos )
| Número de pieza | HMP8191CN | |
| Descripción | NTSC/PAL Video Encoder | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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Data Sheet
HMP8190, HMP8191
May 1999 File Number 4499.1
NTSC/PAL Video Encoder
The HMP8190 and HMP8191 are NTSC and PAL encoders
designed for use in systems requiring the generation of high-
quality NTSC and PAL video.
YCbCr digital video data drive the P0-P15 inputs. The Y data
is optionally lowpass filtered to 6MHz and drives the Y
analog output. Cb and Cr are each lowpass filtered to
1.3MHz, quadrature modulated, and added together. The
result drives the C analog output. The digital Y and C data
are also added together and drive the composite analog
output.
The DACs can drive doubly-terminated (37.5Ω) lines, and
run at a 2x oversampling rate to simplify the analog output
filter requirements.
Applications
• DVD Players
• Video CD Players
• Digital VCRs
• Multimedia PCs
Related Products
- NTSC/PAL Encoders
- HMP8154, HMP8156A
- HMP8170 – HMP8173
• NTSC/PAL Decoders
HMP8115, HMP8116
Features
• (M) NTSC and (B, D, G, H, I, M, N, NC) PAL Operation
• BT.601 and Square Pixel Operation
• Digital Input Formats
- 8-Bit, 16-Bit 4:2:2 YCbCr
- 8-Bit BT.656
• Composite and Y/C Analog Outputs
• Flexible Video Timing Control
- Timing Master or Slave
- Selectable Polarity on Each Control Signal
- Programmable Blank Output Timing
• “Sliced” VBI Data Support
- Closed Captioning
- Widescreen Signalling (WSS)
• Three 2x Oversampling, 10-Bit DACs
- Fast I2C Interface
Ordering Information
PART NUMBER
HMP8190CN
MACROVISION
v7.01
No
TEMP. RANGE (oC)
0 to 70
PACKAGE
64 Ld PQFP (Note 2)
PKG. NO.
Q64.14x14
HMP8191CN (Note 1)
Yes
0 to 70
64 Ld PQFP (Note 2) Q64.14x14
HMP8190EVAL1 (Note 3)
Daughter Card Evaluation Platform.
NOTES:
1. The HMP8191 may be purchased by Macrovision Authorized Buyers only. This device is protected by U.S. patent numbers 4,631,603,
4,577,216, and 4,819,098, and other intellectual property rights. The use of Macrovision’s copy protection technology in the device must be
authorized by Macrovision and is intended for home and other limited pay-per-view uses only, unless otherwise authorized in writing by
Macrovision. Reverse engineering or disassembly is prohibited.
2. PQFP is also known as QFP and MQFP.
3. Evaluation board descriptions are in the Applications section.
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1 page  
HMP8190, HMP8191
CLK2
P8-P15 Cb 2 Y 2 Cr 2 Y 3 Cb 4 Y 4
“FF” "00" “00” EAV
“10” “80” “10”
BLANK
(OUTPUT)
FIGURE 3. PIXEL INPUT TIMING - BT.656
TABLE 3. BT.656 EAV AND SAV SEQUENCES
PIXEL INPUT
P15 P14 P13 P12
Preamble Word 1
1111
Preamble Word 2
0000
Preamble Word 3
0000
Status Word
1 FVH
NOTE:
F: 0 = Field 1; 1 = Field 2
V: 0 = Active Line; 1 = Vertical Blanking
H: 0 = Start Active Video; 1 = End Active Video
P3 - P0: Protection bits; Ignored
P11
1
0
0
P3
P10
1
0
0
P2
P9
1
0
0
P1
P8
1
0
0
P0
Video Timing Control
The pixel input data and the output video timing of the
HMP8190/HMP8191 are at 50 or 59.94 fields per second
interlaced. The timing is controlled by the BLANK, HSYNC,
VSYNC, FIELD, and CLK2 pins.
HSYNC, VSYNC, and Field Timing
The leading edge of HSYNC indicates the beginning of a
horizontal sync interval. If HSYNC is an output, it is asserted
for about 4.7µs. If HSYNC is an input, it must be active for at
least two CLK2 periods. The width of the analog horizontal
sync tip is determined from the video standard and does not
depend on the width of HSYNC.
The leading edge of VSYNC indicates the beginning of a
vertical sync interval. If VSYNC is an output, it is asserted for
3 scan lines in (MM) NTSC and (M, N) PAL modes or 2.5
scan lines in (B, D, G, H, I, NC) PAL modes. If VSYNC is an
input, it must be asserted for at least two CLK2 periods.
When HSYNC and VSYNC are configured as outputs, their
leading edges will occur simultaneously at the start of an
odd field. At the start of an even field, the leading edge of
VSYNC occurs in the middle of the line.
When HSYNC and VSYNC are configured as inputs, the
HMP8190/HMP8191 provides a programmable HSYNC
window for determining FIELD. The window is specified with
respect to the leading or trailing edge of VSYNC. The edge
is selected in the field control register. When HSYNC is
found inside the window, then the encoder sets FIELD to the
value specified in the field control register.
The HMP8190/HMP8191 provides programmable timing for
the VSYNC input. At the active edge of VSYNC, the encoder
resets its vertical half-line counter to the value specified by
the field control register. This allows the input and output
syncs to be offset, although the data must still be aligned.
The FIELD signal is always an output and changes state
near each leading edge of VSYNC. The delay between the
syncs and FIELD depends on the encoder’s operating mode
as summarized in Table 4. In modes in which the encoder
uses CLK to gate its inputs and outputs, the FIELD signal
may be delayed 0-12 additional CLK2 periods.
TABLE 4. FIELD OUTPUT TIMING
OPERATING MODE
SYNC I/O BLANK I/O CLK2
DIRECTION DIRECTION DELAY
COMMENTS
Input
Input
148 FIELD lags VSYNC switch-
ing from odd to even.
FIELD lags the earlier of
VSYNC and HSYNC when
syncs are aligned when
switching from even to odd.
Input
Output
138 FIELD lags VSYNC.
Output Don’t Care 32 FIELD leads VSYNC.
Figure 4 illustrates the HSYNC, VSYNC, and FIELD general
timing for (M) NTSC and (M, N) PAL. Figure 5 illustrates the
general timing for (B, D, G, H, I, NC) PAL. In the figures, all
the signals are shown active low (their reset state), and
FIELD is low during odd fields.
5
5 Page 
HMP8190, HMP8191
TABLE 9. WIDESCREEN SIGNALLING MODES
WSS REGISTERS
WSS
ENABLE BITS
OUTPUT LINE(S)
283A, 283B,
CRC283
20A, 20B,
CRC20
00 None
Ignored
Ignored
01 20 (NTSC)
17 (M PAL)
23 (Other PAL)
Ignored
WSS Data
10 283 (NTSC)
280 (M PAL)
336 (Other PAL)
WSS Data
Ignored
11 20, 283 (NTSC)
17, 280 (M PAL)
23, 336 (Other PAL)
WSS Data
WSS Data
NOTE: The CRC registers are always ignored during PAL operation.
WRITE STATUS BIT
283
Always 1
Always 1
20
Always 1
0 = Loaded
1 = Output
0 = Loaded
1 = Output
Always 1
0 = Loaded
1 = Output
0 = Loaded
1 = Output
TABLE 10. BT.656 ANCILLARY DATA FORMAT FOR PHINC DATA
PIXEL INPUT
P15 P14 P13 P12 P11 P10
Preamble 1
000000
Preamble 2
111111
Preamble 3
111111
Data ID
EP# EP
1
1
0
1
Data Block Number
EP# EP
0
0
0
0
Data Word Count
EP# EP
0
0
0
0
HPLL
Increment
(4 Nibbles)
EP# EP
EP# EP
EP# EP
0
0
0
0
bit 15
bit 14
0
bit 11
bit 10
0 bit 7 bit 6
EP# EP
0
0 bit 3 bit 2
FSCPLL
Increment
(8 Nibbles)s
EP#
EP PSW
0
bit 31
bit 30
EP# EP
F2
F1
bit 27
bit 26
...
EP# EP
0
0 bit 7 bit 6
EP# EP
0
0 bit 3 bit 2
CRC
P14#
X
X
X
X
X
NOTE:
The even parity (EP and EP#) bits are ignored.
HPLL, PSW, F2, and F1 are ignored.
X = Don’t Care.
P9
0
1
1
0
0
1
bit 13
bit 9
bit 5
bit 1
bit 29
bit 25
bit 5
bit 1
X
P8
0
1
1
1
1
1
bit 12
bit 8
bit 4
bit 0
bit 28
bit 24
bit 4
bit 0
X
11
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