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PDF HMPVIDEVALISA Data sheet ( Hoja de datos )
| Número de pieza | HMPVIDEVALISA | |
| Descripción | NTSC/PAL Video Decoder | |
| Fabricantes | Intersil Corporation | |
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HMP8115
April 1998
NTSC/PAL Video Decoder
Features
• (M) NTSC and (B, D, G, H, I, M, N, NC) PAL Operation
- Optional Auto Detect of Video Standard
- ITU-R BT.601 (CCIR601) and Square Pixel Operation
• Digital Output Formats
- VMI Compatible
- 8-Bit, 16-Bit 4:2:2 YCbCr
- 15-Bit (5,5,5), 16-Bit (5,6,5) RGB
- Linear or Gamma-Corrected
- 8-Bit BT.656
• Analog Input Formats
- Three Analog Composite Inputs
- Analog Y/C (S-Video) Input
• “Sliced” VBI Data Capture Capabilities
- Closed Captioning
- Widescreen Signalling (WSS)
- BT.653 System B, C and D Teletext
- NABTS (North American Broadcast Teletext)
- WST (World System Teletext)
• 2-Line (1H) Comb Filter Y/C Separator
• Fast I2C Interface
• Two 8-Bit ADCs
Description
The HMP8115 is a high quality NTSC and PAL decoder with
internal A/D converters. It is compatible with NTSC M, PAL
B, D, G, H, I, M, N, and combination N (NC) video standards.
Both composite and S-video (Y/C) input formats are sup-
ported. A 2-line comb filter plus a user-selectable chromi-
nance trap filter provide high quality Y/C separation. User
adjustments include brightness, contrast, saturation, hue,
and sharpness.
Data during the vertical blanking interval (VBI), such as
closed captioning, widescreen signalling and teletext, may
be captured and output as BT.656 ancillary data. Closed
captioning and widescreen signalling information may also
be read out via the I2C interface.
Ordering Information
TEMP.
PART NUMBER RANGE (oC) PACKAGE
PKG. NO.
HMP8115CN
0 to 70 80 Ld PQFP Q80.14x20
HMPVIDEVAL/ISA Evaluation Board: ISA Frame Grabber
NOTES:
1. PQFP is also known as QFP and MQFP.
2. Evaluation Board and Reference Design descriptions are in the
Applications section.
Applications
• Multimedia PCs
• Video Conferencing
• Video Compression Systems
• Video Security Systems
• LCD Projectors and Overhead Panels
• Related Products
- NTSC/PAL Encoders: HMP815x, HMP817x
- NTSC/PAL Decoders: HMP8112A
• Related Literature
- AN9644: Composite Video Separation Techniques
- AN9716: Widescreen Signalling
- AN9717: YCbCr to RGB Considerations
- AN9728: BT.656 Video Interface for ICs
- AN9738: VMI Video Interface for ICs
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 1
File Number 4283.5
1 page  
HMP8115
Introduction
The HMP8115 is designed to decode baseband composite
or S-video NTSC and PAL signals, and convert them to
either digital YCbCr or RGB data. In addition to performing
the basic decoding operations, the HMP8115 includes hard-
ware to decode different types of VBI data and to generate
digital video patterns for a blue screen, black screen and full
screen color bars.
The digital PLLs are designed to synchronize to all NTSC
and PAL standards. A chroma PLL is used to maintain
chroma lock for demodulation of the color information; a line-
locked PLL is used to maintain vertical spatial alignment.
The PLLs are designed to maintain lock even in the event of
VCR headswitches and multipath noise.
The HMP8115 contains two 8-bit A/D converters and an I2C
interface for programming internal registers.
External Video Processing
Before a video signal can be digitized the decoder has some
external processing considerations that need to be
addressed. This section discusses those external aspects of
the HMP8115.
inside the decoder as determined by bits 7 and 6 of the
COLOR PROCESSING register 06H. In addition to the inter-
nal AGC, the designer can also apply some gain to the
chroma before it reaches the internal AGC logic. This gain is
controlled by pin 28. The voltage at this pin determines the
gain of the chroma before it gets digitized by the chroma A/D
with a typical gain performance as shown in Figure 2.
7
TEMPERATURE = 25oC
6 VCC = 5V
5
4
3
2
1
0
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4
CONTROL VOLTAGE ON THE GAIN_CTRL PIN
ANALOG VIDEO INPUTS
The HMP8115 supports either three composite or two com-
posite and one S-video input.
FIGURE 2. CHROMINANCE AMPLIFIER GAIN
Digitization of Video
Three analog video inputs (NTSC/PAL 1-3) are used to
select which one of three composite video sources are to be
decoded. To support S-video applications, the Y channel
drives the NTSC/PAL 3 analog input, and the C channel
drives the C analog input.
The analog inputs must be AC-coupled to the video signals,
as shown in the Applications section.
ANTI-ALIASING FILTERS
An external anti-alias filter is required to achieve optimum
performance and prevent high frequency components from
being aliased back into the video image.
For the NTSC/PAL 1-3 inputs, a single filter is connected
between the YOUT and YIN pins. For the C input, the anti-
aliasing filter should be connected before the C input. A rec-
ommended filter is shown in Figure 1.
YOUT
R1
332
C1
33pF
L1
8.2µH
C2
82pF
YIN
R2
4.02K
FIGURE 1. RECOMMENDED ANTI-ALIASING FILTER
S-VIDEO CHROMA GAIN CONTROL
The Chroma portion of S-video is AC coupled through an
anti-aliasing filter as shown in the applications section.
Unlike the composite/luma inputs, the Automatic Gain Con-
trol (AGC) for the chroma portion of S-video is done digitally
Prior to A/D conversion, the video signal is DC restored and
gained to generate known video levels into the digital pro-
cessing logic. This process is addressed in the “AGC and
DC Restoration” section. After digitization, sample rate con-
verters and a comb filter are used to perform color separa-
tion and demodulation.
A/D CONVERSION
Video data is sampled at the CLK2 frequency then pro-
cessed by the input sample rate converter. The output levels
of the ADC after AGC processing are:
(M) NTSC
(M, N) PAL
(B, D, G, H, I, NC)
PAL
white
black
blank
sync
224
76
64
0
213
64
64
0
AGC AND DC RESTORATION
The AGC amplifier attenuates or amplifies the analog video
signal to ensure that the sync tip level generates code 0. The
difference from the ideal sync tip level of 0 is used to control
the amount of attenuation or gain of the analog video signal.
The capacitor on the LAGC_CAP pin is used to store the
voltage which sets the gain level of the input video amplifier.
DC restoration positions the video signal such that the DC
level of the back porch generates an average code 64. The
back porch is sampled to determine the average value. The
capacitor on the L_CAP pin is used to store the voltage
5
5 Page 
HMP8115
NTSC M
PAL B, D, G, H, I, N, NC
LINES 1 - 22 NOT ACTIVE
240 ACTIVE LINES
PER FIELD
(LINES 23-262)
480 ACTIVE
LINES / FRAME
(NTSC, PAL M) LINES 263 - 284 NOT ACTIVE
ODD FIELD
SYNC AND
BACK
PORCH
VERTICAL
BLANKING
EVEN FIELD
LINES 1 - 22 NOT ACTIVE
288 ACTIVE LINES
PER FIELD
(LINES 23 - 310)
LINES 311 - 335 NOT ACTIVE
576 ACTIVE
LINES / FRAME
(PAL)
240 ACTIVE LINES
PER FIELD
(LINES 285 - 524)
LINE 525
NOT ACTIVE
FRONT
PORCH
NUMBER OF PIXELS
RECTANGULAR (SQUARE)
NTSC
PAL
288 ACTIVE LINES
PER FIELD
(LINES 336 - 623)
LINES 624-625
NOT ACTIVE
NOTE:
TOTAL PIXELS
ACTIVE PIXELS
858 (780)
720 (640)
864 (944)
720 (768)
TOTAL PIXELS
ACTIVE PIXELS
7. The line numbering for PAL (M) followings NTSC (M) line count minus 3 per the video standards.
FIGURE 9. TYPICAL ACTIVE VIDEO REGIONS
PIN NAME
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
8-BIT, 4:2:2, YCbCr
0
0
0
0
0
0
0
0
Y0, Cb0, Cr0
Y1, Cb1, Cr1
Y2, Cb2, Cr2
Y3, Cb3, Cr3
Y4, Cb4, Cr4
Y5, Cb5, Cr5
Y6, Cb6, Cr6
Y7, Cb7, Cr7
TABLE 3. PIXEL OUTPUT FORMATS
16-BIT, 4:2:2, YCbCr 15-BIT, RGB, (5,5,5)
Cb0, Cr0
Cb1, Cr1
Cb2, Cr2
Cb3, Cr3
Cb4, Cr4
Cb5, Cr5
Cb6, Cr6
Cb7, Cr7
B0
B1
B2
B3
B4
G0
G1
G2
Y0 G3
Y1 G4
Y2 R0
Y3 R1
Y4 R2
Y5 R3
Y6 R4
Y7 0
16-BIT, RGB, (5,6,5)
B0
B1
B2
B3
B4
G0
G1
G2
G3
G4
G5
R0
R1
R2
R3
R4
BT.656
0
0
0
0
0
0
0
0
YCbCr Data,
Ancillary Data,
SAV and EAV
Sequences
PIXEL OUTPUT PORT
Pixel data is output via the P0-P15 pins. Refer to Table 3 for
the output pin definition as a function of the output mode.
8-BIT YCbCr OUTPUT
The DVALID output pin may be configured to operate in one
of two ways. The configuration is determined by the
DVLD_LTC bit (bit 4) of the GENLOCK CONTROL register
04H.
If DVLD_LTC=0, the DVALID output is continuously asserted
during the entire active video time on active scan lines if CLK2
is exactly 2x the desired output sample rate. DVALID being
asserted indicates valid pixel data is present on the P15-P8
pixel outputs. DVALID is never asserted during the blanking
intervals. Refer to Figure 10.
If DLVD_LTC=1, DVALID has the same internal timing as the
first mode, but is ANDed with the CLK2 signal, and the result
is output onto the DVALID pin. This results in a gated CLK2
signal being output during the active video time on active
scan lines. Refer to Figure 11.
If 8-bit YCbCr data is generated, it is output following each
rising edge of CLK2. The YCbCr data is multiplexed as [Cb Y
Cr Y′ Cb Y Cr Y′...], with the first active data each scan line
containing Cb data. The pixel output timing is shown in Fig-
ures 10 and 11.
BLANK, HSYNC, VSYNC, DVALID, VBIVALID, and FIELD
are output following the rising edge of CLK2. When BLANK
is asserted and VBIVALID is deasserted, the YCbCr outputs
have a value of 16 for Y and 128 for Cb and Cr.
11
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