DataSheet.es    


PDF HMS30C7202 Data sheet ( Hoja de datos )

Número de pieza HMS30C7202
Descripción 32-bit ARM7TDMI RISC static CMOS CPU core
Fabricantes Hynix Semiconductor　
Logotipo Hynix Semiconductor Logotipo



Hay una vista previa y un enlace de descarga de HMS30C7202 (archivo pdf) en la parte inferior de esta página.


Total 30 Páginas

No Preview Available ! HMS30C7202 Hoja de datos, Descripción, Manual

HMS30C7202
Highly-integrated MPU
(ARM Based 32-Bit Microprocessor)
Datasheet
Version 1.4
Hynix Semiconductor Inc.

1 page




HMS30C7202 pdf
HMS30C7202
FEATURES
„ 32-bit ARM7TDMI RISC static CMOS CPU core : Running up to 70 MHz
„ 8Kbytes combined instruction/data cache
„ Memory management unit
„ Supports Little Endian operating system
„ 2Kbytes SRAM for internal buffer memory
„ On-chip peripherals with individual power-down:
- Multi-channel DMA
- 4 Timer Channels with Watch Dog Timer
- Intelligent Interrupt Controller
- Memory controller for ROM, Flash, SRAM, SDRAM
- Power management unit
- LCD Controller for mono/color STN and TFT LCD
- Real-time clock (32.768kHz oscillator)
- Infrared communications (SIR support)
- 4 UARTs (16C550 compatible)
- PS/2 External Keyboard / Mouse interface
- 2 Pulse-Width-Modulated (PWM) interface
- Matrix Keyboard control interface (8*8)
- GPIO
- MMC / SMC Card interface
- 2 Controller Area Network (CAN)
- USB (slave)
- On-chip ADC and interface module (Battery Check, Audio In, Touch Panel)
- On-chip DAC and interface module (8 Bit Stereo Audio Output)
- 3 PLLs
Figure A. Functional Block Diagram
„ JTAG debug interface and boundary scan
„ 0.25um Low Power CMOS Process
„ 2.5V internal / 3.3V IO supply voltage
„ 256-pin MQFP / FBGA package
„ Low power consumption
© 2002 Hynix Semiconductor Inc. All Rights Reserved.
-v-
Version 1.4

5 Page





HMS30C7202 arduino
HMS30C7202
10.2.3.24 Interrupt Pending 1 Register ............................................................................................................. 112
10.2.3.25 Interrupt Pending 2 Register ............................................................................................................. 112
10.2.3.26 Message Valid 1 Register.................................................................................................................. 112
10.2.3.27 Message Valid 2 Register.................................................................................................................. 112
10.3 GPIO ................................................................................................................................................................ 114
10.3.1 External Signals........................................................................................................................................ 114
10.3.2 Registers ................................................................................................................................................... 114
10.3.2.1 ADATA............................................................................................................................................. 115
10.3.2.2 ADIR ................................................................................................................................................ 115
10.3.2.3 AMASK............................................................................................................................................ 116
10.3.2.4 ASTAT.............................................................................................................................................. 116
10.3.2.5 AEDGE ............................................................................................................................................ 116
10.3.2.6 ACLR ............................................................................................................................................... 116
10.3.2.7 APOL................................................................................................................................................ 116
10.3.2.8 GPIO PORT A Enable Register ........................................................................................................ 116
10.3.2.9 BDATA ............................................................................................................................................. 117
10.3.2.10 BDIR ................................................................................................................................................ 117
10.3.2.11 BMASK............................................................................................................................................ 117
10.3.2.12 BSTAT .............................................................................................................................................. 117
10.3.2.13 BEDGE............................................................................................................................................. 117
10.3.2.14 BCLK ............................................................................................................................................... 117
10.3.2.15 BPOL................................................................................................................................................ 117
10.3.2.16 GPIO PORT B Enable Register ........................................................................................................ 117
10.3.2.17 CDATA ............................................................................................................................................. 117
10.3.2.18 CDIR ................................................................................................................................................ 117
10.3.2.19 CMASK............................................................................................................................................ 118
10.3.2.20 CBSTAT ........................................................................................................................................... 118
10.3.2.21 CEDGE............................................................................................................................................. 118
10.3.2.22 CCLK ............................................................................................................................................... 118
10.3.2.23 CPOL................................................................................................................................................ 118
10.3.2.24 GPIO PORT C Enable Register ........................................................................................................ 118
10.3.2.25 DDATA............................................................................................................................................. 118
10.3.2.26 DDIR ................................................................................................................................................ 118
10.3.2.27 DMASK............................................................................................................................................ 118
10.3.2.28 DBSTAT ........................................................................................................................................... 118
10.3.2.29 DEDGE ............................................................................................................................................ 118
10.3.2.30 DCLK ............................................................................................................................................... 118
10.3.2.31 DPOL................................................................................................................................................ 118
10.3.2.32 GPIO PORT D Enable Register ........................................................................................................ 118
10.3.2.33 EDATA ............................................................................................................................................. 119
10.3.2.34 EDIR................................................................................................................................................. 119
10.3.2.35 EMASK ............................................................................................................................................ 119
10.3.2.36 EBSTAT............................................................................................................................................ 119
10.3.2.37 EEDGE............................................................................................................................................. 119
10.3.2.38 ECLK................................................................................................................................................ 119
10.3.2.39 EPOL ................................................................................................................................................ 119
10.3.2.40 GPIO PORT E Enable Register ........................................................................................................ 119
10.3.2.41 Tic Test mode Register(TICTMDR) ................................................................................................. 119
10.3.2.42 PORTA Multi-function Select register(AMULSEL)......................................................................... 120
10.3.2.43 SWAP Pin Configuration Register(SWAP)....................................................................................... 120
10.3.3 GPIO Interrupt ......................................................................................................................................... 120
10.3.4 GPIO Rise/Fall Time ................................................................................................................................ 121
10.4 INTERRUPT CONTROLLER................................................................................................................................... 122
10.4.1 Block diagram .......................................................................................................................................... 122
10.4.2 Registers ................................................................................................................................................... 122
10.4.2.1 Interrupt Enable Register (IER) ........................................................................................................ 123
10.4.2.2 Interrupt Status Register (ISR).......................................................................................................... 124
10.4.2.3 IRQ Vector Register (IVR) ............................................................................................................... 125
10.4.2.4 Source Vector Register (SVR0 to SVR30)........................................................................................ 125
10.4.2.5 Interrupt ID Register (IDR) .............................................................................................................. 125
© 2002 Hynix Semiconductor Inc. All Rights R5eserved.
-5-
Version 1.4

11 Page







PáginasTotal 30 Páginas
PDF Descargar[ Datasheet HMS30C7202.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
HMS30C720232-bit ARM7TDMI RISC static CMOS CPU coreHynix Semiconductor
Hynix Semiconductor
HMS30C720232-Bit MicroprocessorHynix Semiconductor
Hynix Semiconductor
HMS30C720232-Bit MPUMagnaChip Semiconductor
MagnaChip Semiconductor
HMS30C7202N32-Bit MPUMagnaChip Semiconductor
MagnaChip Semiconductor

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

 Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

 Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar