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PDF HMU17GM-45883 Data sheet ( Hoja de datos )
| Número de pieza | HMU17GM-45883 | |
| Descripción | 16 x 16-Bit CMOS Parallel Multiplier | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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HMU17/883
October 1997
16 x 16-Bit CMOS Parallel Multiplier
Features
Description
• This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• 16 x 16-Bit Parallel Multiplier with Full 32-Bit Product
• High-Speed (45ns) Clocked Multiply Time
• Low Power CMOS Operation
- ICCSB = 500µA Maximum
- ICCOP = 7.0mA Maximum at 1MHz
• HMU17/883 is Compatible with the AM29517, LMU17,
IDT7217, and the CY7C517
• Supports Two’s Complement, Unsigned Magnitude
and Mixed Mode Multiplication
• TTL Compatible Inputs/Outputs
- Three-State Output
Ordering Information
TEMP.
PART NUMBER RANGE (oC)
PACKAGE
HMU17GM-45/883 -55 to 125 68 Ld PGA
HMU17GM-60/883 -55 to 125 68 Ld PGA
PKG.
NO.
The HMU17/883 is a high speed, low power CMOS 16 x 16-bit
parallel multiplier ideal for fast, real time digital signal processing
applications. The 16-bit X and Y operands may be independently
specified as either two’s complement or unsigned magnitude for-
mat, thereby allowing mixed mode multiplication operations.
Additional inputs are provided to accommodate format adjust-
ment and rounding of the 32-bit product. The Format Adjust con-
trol allows the user the option of selecting a 31-bit product with
the sign bit replicated LSP. The Round control is provided to
accommodate rounding of the most significant portion of the
result. This is accomplished by adding one to the most signifi-
cant bit of the LSP.
Two 16-bit output registers (MSP and LSP) are provided to hold
the most and least significant portions of the result, respectively.
These registers may be made transparent for asynchronous
operation through the use of the Feedthrough Control (FT). The
two halves of the product may be routed to a single 16-bit three-
state output port via the output multiplexer control, and in addi-
tion, the LSP is connected to the Y-input port through a separate
three-state buffer.
The HMU17/883 utilizes a single clock signal (CLK) along with
three register enables (ENX, ENY, and ENP) to latch the input
operands and the output product registers. The ENX and ENY
inputs enable the X and Y input registers, while ENP enables both
the LSP and MSP output registers. This configuration facilitates
the use of the HMU17/883 for micro-programmed systems.
All outputs of the HMU17/883 also offer three-state control for
multiplexing onto multiuse system busses.
Functional Block Diagram
X0-15 TCX
REGISTER
CLK
ENX
ENY
FA
FT
ENP
MSPSEL
OEP
RND
TCY Y0-15/P0-15
REGISTER
REGISTER
OEL
MULTIPLIER ARRAY
FORMAT ADJUST
MSP
LSP
REGISTER REGISTER
MULTIPLEXER
P16-31/P0-15
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
3-36
File Number 2805.2
1 page  
HMU17/883
Burn-In Circuit
11 N/C X13 X15 RND TCY VCC GND FT OEP
MSP
10 X11 X12 X14 (ENX) TCX VCC GND SEL FA (ENP) N/C
9 X9 X10
8 X7
X8
7 X5
X6
6 X3
X4
5 X1
X2
68 LEAD
PIN GRID ARRAY
TOP VIEW
P30/ P31/
P14 P15
P28/ P29/
P12 P13
P26/ P27/
P10 P11
P24/ P25/
P8 P9
P22/ P23/
P6 P7
4 OEL X0
P20/ P21/
P4 P5
3 (ENY) CLK
P18/ P19/
P2 P3
2
N/C
Y0/P0 Y2/P2 Y4/P4 Y6/P6 Y8/P8
Y10/
P10
Y12/
P12
Y14/ P16/
P14 P0
P17/
P1
1
Y1/P1 Y3/P3 Y5/P5 Y7/P7 Y9/P9
Y11/
P11
Y13/
P13
Y15/
P15
N/C
A B CD E F GH J K L
PGA
PIN
PIN BURN-IN PGA
NAME SIGNAL PIN
PIN BURN-IN PGA
NAME SIGNAL PIN
PIN BURN-IN PGA
NAME SIGNAL PIN
B6
X4
F6
F1
Y9/P9
F11
K7 P10/P26 VCC/2 E11
A6
X3
F5
G2 Y10/P10 F12
L7 P11/P27 VCC/2 D10
B5
X2
F4
G1 Y11/P11 F13
K8 P12/P28 VCC/2 D11
A5
X1
F3
H2 Y12/P12 F14
L8 P13/P29 VCC/2 C10
B4
X0
F2
H1 Y13/P13 F15
K9 P14/P30 VCC/2 C11
A4
OEL
VCC
J2 Y14/P14 F4
L9 P15/P31 VCC/2 B10
B3 CLK F0
J1 Y15/P15 F5 K10 ENP F0 A10
A3 ENY F0
K2 P0/P16 VCC/2 K11
OEP
F1
B9
B2 Y0/P0 F2
L2 P1/P17 VCC/2 J10 FA F14 A9
B1 Y1/P1 F3
K3 P2/P18 VCC/2 J11 FT F15 B8
C2 Y2/P2 F4
L3 P3/P19 VCC/2 H10 MSPSEL F14
A8
C1 Y3/P3 F5
K4
P4/P20 VCC/2
H11
GND
GND
B7
D2 Y4/P4 F6
L4
P5/P21 VCC/2
G10
GND
GND
A7
D1 Y5/P5 F7
K5 P6/P22 VCC/2 G11
VCC
VCC
A2
E2 Y6/P6 F8
L5 P7/P23 VCC/2 F10
VCC
VCC
K1
E1 Y7/P7 F9
K6 P8/P24 VCC/2 F11 TCY F15 L10
F2
Y8/P8
F10
L6 P9/P25 VCC/2 E10 TCX F15 B11
NOTES:
11. VCC = 5.0V +0.5V/-0.0V with 0.1µF decoupling capacitor to GND.
12. F0 = 100kHz, F1 = F0/2, F2 = F1/2, . . . . . . . . .
13. VIH = VCC 1V ±0.5V (Min), VIL = 0.8V (Max).
14. 47kΩ load resistors used on all pins except VCC and GND (Pin Grid identifiers F10, G10, G11 and H11).
PIN
NAME
RND
ENX
X15
X14
X13
X12
X11
X10
X9
X8
X7
X6
X5
N.C.
N.C.
N.C.
N.C.
BURN-IN
SIGNAL
F1
F0
F3
F2
F15
F14
F13
F12
F11
F10
F9
F8
F7
NONE
NONE
NONE
NONE
3-40
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| PDF Descargar | [ Datasheet HMU17GM-45883.PDF ] | |
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