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PDF HN58S65A Data sheet ( Hoja de datos )
| Número de pieza | HN58S65A | |
| Descripción | 64 k EEPROM (8-kword x 8-bit) Ready/Busy function | |
| Fabricantes | Hitachi Semiconductor | |
| Logotipo |  |
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HN58S65A Series
64 k EEPROM (8-kword × 8-bit)
Ready/Busy function
ADE-203-691A (Z)
Preliminary
Rev. 0.3
Nov. 1997
Description
The Hitachi HN58S65A series is electrically erasable and programmable ROM organized as 8192-word
× 8-bit. It has realized high speed, low power consumption and high reliability by employing advanced
MNOS memory technology and CMOS process and circuitry technology. They also have a 64-byte
page programming function to make their write operations faster.
Features
• Single supply: 2.2 to 3.6 V
• Access time: 150 ns (max)
• Power dissipation
Active: 10 mW/MHz (typ)
Standby: 36 µW (max)
• On-chip latches: address, data, CE, OE, WE
• Automatic byte write: 15 ms (max)
• Automatic page write (64 bytes): 15 ms (max)
• Ready/Busy
• Data polling and Toggle bit
• Data protection circuit on power on/off
• Conforms to JEDEC byte-wide standard
• Reliable CMOS with MNOS cell technology
• 105 erase/write cycles (in page mode)
• 10 years data retention
• Software data protection
• Industrial versions (Temperature range: – 40 to + 85˚C) are also available.
Preliminary: This document contains information on a new product. Specifications and information
contained herein are subject to change without notice.
1 page  
Capacitance (Ta = 25˚C, f = 1 MHz)
Parameter
Symbol
Min
Typ
Input capacitance
Cin*1
——
Output capacitance
Cout*1
—
—
Note: 1. This parameter is sampled and not 100% tested.
Max
6
12
HN58S65A Series
Unit Test conditions
pF Vin = 0 V
pF Vout = 0 V
AC Characteristics (Ta = 0 to + 70˚C, VCC = 2.2 to 3.6 V)
Test Conditions
• Input pulse levels : 0.4 V to 2.4 V (VCC = 2.7 to 3.6 V), 0.4 V to 1.9 V (VCC = 2.2 to 2.7 V)
• Input rise and fall time : ≤ 5 ns
• Input timing reference levels : 0.8, 1.8 V
• Output load : 1TTL Gate +100 pF
• Output reference levels : 1.5 V, 1.5 V (VCC = 2.7 to 3.6 V)
1.1 V, 1.1 V (VCC = 2.2 to 2.7 V)
Read Cycle
HN58S65A
-15
Parameter
Symbol Min
Max
Address to output delay
CE to output delay
OE to output delay
Address to output hold
OE (CE) high to output float*1
t ACC
t CE
t OE
t OH
t DF
—
—
10
0
0
150
150
80
—
80
Unit
ns
ns
ns
ns
ns
Test conditions
CE = OE = VIL, WE = VIH
OE = VIL, WE = VIH
CE = VIL, WE = VIH
CE = OE = VIL, WE = VIH
CE = VIL, WE = VIH
5 Page 
Page Write Timing Waveform(2) (CE Controlled)
*6
Address
A0 to A12
CE
WE
OE
tAS tAH
tCW
tDL
tWS tWH
tOES
tDS
tDH
Din
RDY/Busy
High-Z
tDB
tBLC
Data Polling Timing Waveform
Address
An
CE
An
WE
OE
I/O7
tOEH tCE*7
Din X
tOE*7
Dout X
tWC
HN58S65A Series
tBL
tOEH
tWC
tDW
High-Z
An
tOES
tDW
Dout X
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet HN58S65A.PDF ] | |
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