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HN58V1001FP-25 PDF даташит

Спецификация HN58V1001FP-25 изготовлена ​​​​«Hitachi Semiconductor» и имеет функцию, называемую «1M EEPROM (128-kword x 8-bit) Ready/Busy and RES function».

Детали детали

Номер произв HN58V1001FP-25
Описание 1M EEPROM (128-kword x 8-bit) Ready/Busy and RES function
Производители Hitachi Semiconductor
логотип Hitachi Semiconductor логотип 

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HN58V1001FP-25 Даташит, Описание, Даташиты
HN58V1001 Series
1M EEPROM (128-kword × 8-bit)
Ready/Busy and RES function
ADE-203-314G (Z)
Rev. 7.0
Oct. 31, 1997
Description
The Hitachi HN58V1001 is a electrically erasable and programmable ROM organized as 131072-word × 8-
bit. It has realized high speed, low power consumption and high reliability by employing advanced MNOS
memory technology and CMOS process and circuitry technology. It also has a 128-byte page programming
function to make the write operations faster.
Features
Single 3 V supply: 2.7 V to 5.5 V
Access time: 250 ns (max)
Power dissipation
Active: 20 mW/MHz, (typ)
Standby: 110 µW (max)
On-chip latches: address, data, CE, OE, WE
Automatic byte write: 15 ms (max)
Automatic page write (128 bytes): 15 ms (max)
Data polling and RDY/Busy
Data protection circuit on power on/off
Conforms to JEDEC byte-wide standard
Reliable CMOS with MNOS cell technology
104 erase/write cycles (in page mode)
10 years data retention
Software data protection
Write protection by RES pin









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HN58V1001FP-25 Даташит, Описание, Даташиты
HN58V1001 Series
Ordering Information
Type No.
HN58V1001P-25
HN58V1001FP-25
HN58V1001T-25
Access time
250 ns
250 ns
250 ns
Package
600 mil 32-pin plastic DIP (DP-32)
525 mil 32-pin plastic SOP (FP-32D)
8 × 14 mm 32-pin plastic TSOP (TFP-32DA)
Pin Arrangement
HN58V1001P/FP Series
RDY/Busy
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
1 32
2 31
3 30
4 29
5 28
6 27
7 26
8 25
9 24
10 23
11 22
12 21
13 20
14 19
15 18
16 17
(Top view)
VCC
A15
RES
WE
A3
A2
A1
A13 A0
A8
A9
I/O0
I/O1
I/O2
A11
OE
IV/OS3S
A10
CE
I/O4
I/O5
I/O6
I/O7 I/O7
I/O6
I/O5
CE
A10
OE
I/O4
I/O3
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
HN58V1001T Series
(Top view)
16 A4
15 A5
14 A6
13 A7
12 A12
11 A14
10 A16
9 RDY/Busy
8 VCC
7 A15
6 RES
5 WE
4 A13
3 A8
2 A9
1 A11
Pin Description
Pin name
A0 to A16
I/O0 to I/O7
OE
CE
WE
VCC
VSS
RDY/Busy
RES
Function
Address input
Data input/output
Output enable
Chip enable
Write enable
Power supply
Ground
Ready busy
Reset
2









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HN58V1001FP-25 Даташит, Описание, Даташиты
Block Diagram
VCC
VSS
RES
OE
CE
WE
RES
A0
to
A6
A7
to
A16
High voltage generator
Control logic and timing
Address
buffer and
latch
Y decoder
X decoder
HN58V1001 Series
I/O0to I/O7 RDY/Busy
I/O buffer
and
input latch
Y gating
Memory array
Data latch
Operation Table
Operation
CE OE WE RES
Read
Standby
VIL VIL VIH VH*1
VIH ×*2 ×
×
Write
VIL VIH VIL VH
Deselect
VIL VIH VIH VH
Write Inhibit
× × VIH ×
Data Polling
× VIL × ×
VIL VIL VIH VH
Program reset
× × × VIL
Notes: 1. Refer to the recommended DC operating conditions.
2. × : Don’t care
RDY/Busy
High-Z
High-Z
High-Z to VOL
High-Z
VOL
High-Z
I/O
Dout
High-Z
Din
High-Z
Dout (I/O7)
High-Z
3










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