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PDF HN58X24128TI Data sheet ( Hoja de datos )
| Número de pieza | HN58X24128TI | |
| Descripción | Two-wire serial interface/ 128k EEPROM (16-kword x 8-bit)/ 256k EEPROM (32-kword x 8-bit) | |
| Fabricantes | Hitachi Semiconductor | |
| Logotipo |  |
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HN58X24128I/HN58X24256I
Two-wire serial interface
128k EEPROM (16-kword × 8-bit)
256k EEPROM (32-kword × 8-bit)
ADE-203-1029B (Z)
Rev. 2.0
Nov. 26, 1999
Description
HN58X24xxx series are two-wire serial interface EEPROM (Electrically Erasable and Programmable
ROM). They realize high speed, low power consumption and a high level of reliability by employing
advanced MNOS memory technology and CMOS process and low voltage circuitry technology. They also
have a 64-byte page programming function to make their write operation faster.
Note: Hitachi’s serial EEPROM are authorized for using consumer applications such as cellular phone,
camcorders, audio equipment. Therefore, please contact Hitachi’s sales office before using
industrial applications such as automotive systems, embedded controllers, and meters.
Features
• Single supply: 1.8 V to 5.5 V
• Two-wire serial interface (I2CTM serial bus*1)
• Clock frequency: 400 kHz
• Power dissipation:
Standby: 3 µA (max)
Active (Read): 1 mA (max)
Active (Write): 5 mA (max)
• Automatic page write: 64-byte/page
• Write cycle time: 10 ms (2.7 V to 5.5 V)/15 ms (1.8 V to 2.7 V)
• Endurance: 105 Cycles (Page write mode)
• Data retention: 10 Years
1 page  
HN58X24128I/HN58X24256I
AC Characteristics (Ta = –40 to +85˚C, VCC = 1.8 to 5.5 V)
Test Conditions
• Input pules levels:
VIL = 0.2 × VCC
VIH = 0.8 × VCC
• Input rise and fall time: ≤ 20 ns
• Input and output timing reference levels: 0.5 × VCC
• Output load: TTL Gate + 100 pF
Parameter
Symbol Min
Typ Max Unit
Clock frequency
fSCL — — 400 kHz
Clock pulse width low
tLOW 1200 — — ns
Clock pulse width high
t HIGH
600
—
—
ns
Noise suppression time
tI — — 50 ns
Access time
tAA 100 — 900 ns
Bus free time for next mode
tBUF 1200 — — ns
Start hold time
t HD.STA
600
—
—
ns
Start setup time
t SU.STA
600
—
—
ns
Data in hold time
t HD.DAT
0
— — ns
Data in setup time
t SU.DAT
100
—
—
ns
Input rise time
tR — — 300 ns
Input fall time
tF — — 300 ns
Stop setup time
t SU.STO
600
—
—
ns
Data out hold time
tDH 50 — — ns
Write cycle time
VCC = 2.7 V to 5.5 V tWC
—
—
10
ms
VCC = 1.8 V to 2.7 V tWC
—
—
15
ms
Notes: 1. This parameter is sampled and not 100% tested.
2. tWC is the time from a stop condition to the end of internally controlled write cycle.
Notes
1
1
1
2
2
5
5 Page 
HN58X24128I/HN58X24256I
Device Addressing
The EEPROM device requires an 8-bit device address word following a start condition to enable the chip
for a read or a write operation. The device address word consists of 4-bit device code, 3-bit device address
code and 1-bit read/write(R/W) code. The most significant 4-bit of the device address word are used to
distinguish device type and this EEPROM uses “1010” fixed code. The device address word is followed by
the 3-bit device address code in the order of A2, A1, A0. The device address code selects one device out of
all devices which are connected to the bus. This means that the device is selected if the inputted 3-bit
device address code is equal to the corresponding hard-wired A2-A0 pin status. The eighth bit of the
device address word is the read/write(R/W) bit. A write operation is initiated if this bit is low and a read
operation is initiated if this bit is high. Upon a compare of the device address word, the EEPROM enters
the read or write operation after outputting the zero as an acknowledge. The EEPROM turns to a stand-by
state if the device code is not “1010” or device address code doesn’t coincide with status of the correspond
hard-wired device address pins A0 to A2.
Device Address Word
Device address word (8-bit)
Device code (fixed)
128k, 256k 1 0 1 0
Note: 1. R/W=“1” is read and R/W = “0” is write.
Device address code
A2 A1
A0
R/W code*1
R/W
11
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet HN58X24128TI.PDF ] | |
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