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HPMX-2003 PDF даташит

Спецификация HPMX-2003 изготовлена ​​​​«Agilent(Hewlett-Packard)» и имеет функцию, называемую «Silicon Bipolar RFIC 900 MHz Vector Modulator».

Детали детали

Номер произв HPMX-2003
Описание Silicon Bipolar RFIC 900 MHz Vector Modulator
Производители Agilent(Hewlett-Packard)
логотип Agilent(Hewlett-Packard) логотип 

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HPMX-2003 Даташит, Описание, Даташиты
Silicon Bipolar RFIC
900 MHz Vector Modulator
Technical Data
HPMX-2003
Features
• 800–1000 MHz Output
Frequency Range
• +6 dBm Peak Pout
• Unbalanced 50 Output
• Internal 90° Phase Shifter
• 5 Volt, 36 mA Bias
• SO-16 Surface Mount Package
Applications
• Direct Modulator for 900
MHz Cellular Telephone
Handsets, Including GSM,
JDC, and NADC
• Direct Modulator for
900␣ MHz ISM Band Spread-
Spectrum Transmitters and
LANs
Functional Block Diagram
Plastic SO-16 Package
Pin Configuration
VCC 1
VCC 2
GROUND 3
GROUND 4
Qref 5
Qmod 6
LOin 7
LOgnd 8
16 VCCL
15 RFout
14 GROUND
13 GROUND
12 Iref
11 Imod
10 GROUND
9 DO NOT CONNECT
Description
Hewlett Packard’s HPMX-2003 is a
Silicon RFIC direct conversion
vector modulator designed for use
at output frequencies between
800␣ MHz and 1 GHz. Housed in a
SO-16 surface mount plastic pack-
age, the IC contains two matched
Gilbert cell mixers, an RC phase
shifter, a summer, and an output
amplifier complete with 50
impedance match and DC block.
This device is suitable for use in
direct and offset-loop modulated
portable and mobile telephone
handsets for cellular systems such
as GSM, North American Digital
Cellular and Japan Digital Cellu-
lar. It can also be used in digital
transmitters operating in the
900 MHz ISM (Industrial-Scien-
tific-Medical) band, including use
in Local Area Networks (LANs).
Imod
Iref
LO +
LO –
Qref
Qmod
I MIXER
0°
φ ΣPHASE
SHIFTER
SUMMER
90°
OUTPUT
AMPLIFIER
Q MIXER
VCC
VCCL
RFout
50 ZO
unbalanced
The HPMX-2003 is fabricated with
Hewlett-Packard’s 25 GHz
ISOSAT-II process, which
combines stepper lithography,
ion-implantation, self-alignment
techniques, and gold metallization
to produce RFICs with superior
performance, uniformity and
reliability.
5965-9103E
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HPMX-2003 Даташит, Описание, Даташиты
HPMX-2003 Absolute Maximum Ratings, TA = 25°C
Symbol
Pdiss
LOin
VCC
VImod,
VQmod
VIref, VQref
TSTG
Tj
Parameter
Power Dissipation[2,3]
LO Input Power
Supply Voltage
Swing of VImod about VIref[4]
or VQmod about VQref
Reference Input Levels[4]
Storage Temperature
Junction Temperature
Units
mW
dBm
V
Vp-p
Absolute
Maximum[1]
500
15
10
5[4]
V 5[4]
°C -65to+150
°C 150
Thermal Resistance[2]:
θjc =125°C/W
Notes:
1. Operation of this device above any one
of these parameters may cause
permanent damage.
2. TC = 25°C (TC is defined to be the
temperature at the end of pin 3 where it
contacts the circuit board).
3. Derate at 8 mW/°C for TC > 88°C.
4. Do not exceed VCC by more than 0.8 V.
HPMX-2003 Guaranteed Electrical Specifications, TA = 25°C, ZO = 50
VCC = 5 V, LO= -12 dBm at 900 MHz (Unbalanced Input), VIref = VQref = 2.5 V (Unless Otherwise Noted).
Symbol
Parameters and Test Conditions
Units Min. Typ. Max.
Id
Pout
LOleak
εmod
Device Current
mA 36
Output Power
VImod = VQmod = 3.75 V dBm +4.0 +6
Pout - LO at Output
VImod = VQmod= 2.5 V dBc +30 +37
Average
Modulation
Error
(VImod - 2.5)2 + (VQmod - 2.5)2 =1.25V
%
4
44
7
HPMX-2003 Summary Characterization Information, TA = 25°C, ZO = 50
VCC = 5 V, LO = -12 dBm at 900 MHz (Unbalanced Input), VIref = VQref = 2.5 V (Unless Otherwise Noted).
Symbol
Parameters and Test Conditions
Units Typ.
Rin Input Resistance (Imod to Iref or Qmod to Qref)
10 k
Rin-gnd Input Resistance to Ground (Any I, Q Pin to Ground)
10 k
VSWRLO LO VSWR (50 )
GSM: 890-915 MHz Bandwidth
NADC: 824-850 MHz Bandwidth
JDC: 940-960 MHz Bandwidth
1.5:1
1.5:1
1.5:1
VSWRO
Output VSWR (50 ) (Tuned by
Placement of VccL Capacitor –
See Figures 22, 32, and 42)
GSM: 890-915 MHz Bandwidth
NADC: 824-850 MHz Bandwidth
JDC: 940-960 MHz Bandwidth
1.2:1
1.1:1
1.2:1
Output Noise Floor
IM3 DSB Third Order Intermodulation Products
Ai RMS Amplitude Error
Pi RMS Phase Error
VImod = VQmod= 3.75 V
dBm/Hz
dBc
dB
degrees
-134
+34
0.3
2
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HPMX-2003 Даташит, Описание, Даташиты
HPMX-2003 Pin
Description
VCC (pins 1,2)
These two pins provide DC power
to the mixers in the RFIC, and are
connected together internal to the
package. They should be con-
nected to a 5 V supply, with appro-
priate AC bypassing (1000 pF typ.)
used near the pins, as shown in
figures 1 and 2. The voltage on
these pins should always be
kept at least 0.8 V more posi-
tive than the DC level on any
of pins 5, 6, 11, or 12. Failure to
do so may result in the modulator
drawing sufficient current
through the data or reference
inputs to damage the IC.
Ground (pins 3, 4, 10, 13 & 14)
These pins should connect with
minimal inductance to a solid
ground plane (usually the back-
side of the PC board). Recom-
mended assembly employs
multiple plated through via holes
where these leads contact the PC
board.
Iref (pin 12) and Q ref (pin 5),
I␣ (pin 11) and Q (pin 6) Inputs
The I and Q inputs are designed
for unbalanced operation but can
be driven differentially with simi-
lar performance. The recom-
mended level of unbalanced I and
Q signals is 2.5 Vp-p with an aver-
age level of 2.5 V above ground.
The reference pins should be DC
biased to this average data signal
level (VCC/2 or 2.5 V typ.). For
single ended drive, pins 5 and 12
can be tied together. For balanced
operation, 2.5 Vp-p signals may be
applied across the Imod/Iref and the
Qmod/Qref pairs. The average level
of all four signals should be about
2.5 V above ground. The imped-
ance between any I or Q and
ground is typically 10 K and the
impedance between Imod and Iref or
Qmod and Qref is typically 10 K.
The input bandwidth typically
exceeds 40 MHz. It is possible to
reduce LO leakage through the IC
by applying slight DC imbalances
between Imod and Iref and/or Qmod
and Qref (see section entitled
“HPMX-2003 Using Offsets to Im-
prove Lo Leakage”). All perfor-
mance data shown on this data
sheet was taken with unbalanced
I/Q inputs.
LO Input (pins 7 and 8)
The LO input of the HPMX-2003 is
balanced and matched to 50 For
drive from an unbalanced LO, pin
7 should be AC coupled to the LO
using a 50 transmission line and
a blocking capacitor (1000 pF
typ.), and pin 8 should be AC
grounded (1000 pF capacitor
typ.), as shown in figure 1. For
drive from a balanced LO source,
50 transmission lines and block-
ing capacitors (1000 pF typ.) are
used on both pins 7 and 8, as
shown in figure 2. The internal
phase shifter allows operation
from 800 - 1000 MHz. The recom-
mended LO input level is -12 dBm.
All performance data shown on
this data sheet was taken with un-
balanced LO operation.
RF Output (pin15)
The RF output of the HPMX-2003
is configured for unbalanced
operation. The output is internally
DC blocked and matched to 50 ,
so a simple 50 microstrip line is
all that is required to connect the
modulator to other circuits.
VCCL (pin 16)
Pin 16 is the VCC input for the out-
put stage of the IC. It is not inter-
nally connected to the other VCC
pins. The external connection al-
lows the addition of a small induc-
tor (0 - 6 nH) to tune the output
for minimum VSWR, depending
upon the operating frequency.
+5 V
1000 pF
Qref
Qmod
LOin
1000 pF
1000 pF
1000 pF
+5 V
1000 pF
OPTIONAL INDUCTOR
1 16
2 15
3 14
RFout
4 13
5 12
Iref
Qref
6 11
7 10
Imod
LOin+
Qmod
1000 pF
8
9 DO NOT CONNECT
LOin–
1000 pF
1000 pF
OPTIONAL INDUCTOR
1 16
2 15
3 14
RFout
4 13
5 12
6 11
I ref
Imod
7 10
8 9 DO NOT CONNECT
Figure 1. HPMX-2003 Connections Showing Unbalanced LO
and I, Q Inputs.
Figure 2. HPMX-2003 Connections Showing Balanced LO
and I, Q Inputs.
7-40










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